4 Revision History
Changes from Revision * (April 2021) to Revision A (February 2023)
- Changed the VDD11 pin descriptions for clarityGo
- Revised the PDB pin voltage for normal operationGo
- Added a link to Design Requirements under the RIN pinsGo
- Relaxed the VIH specifications of PDB for 3.3-V from 2-V
to 1.17-VGo
- Updated the PDB, XIN/REFCLK, and VDD_SEL VIH and
VIL specifications to be independent of VDDIOGo
- Removed the footnote that 'XIN/REFCLK uses 1.8V logic, but is 3.3V
tolerant' since it is now indicated by the updates to XIN/REFCLK in the
tableGo
- Rewrote the basic synchronized forwarding code example to set both
sensors to use CSI-2 serializersGo
- Added in that the voltage of VI2C must match the voltage
of VVDDIO
Go
- Removed the mention of 'PDB' from register 0x0DGo
- Changed suggested ferrite beads for the PoC Network from 1500 kΩ to
1.5 kΩ Go
- Changed the recommended PoC network impedance recommendation from
2kΩ to 1kΩGo
- Updated the PoC system descriptionGo
- Removed the insertion and return loss values from the table on
Suggested Characteristics for Single-Ended PCB Traces With Attached PoC
NetworksGo
- Changed the pull-up resistor for PDB from 33-kΩ to 10-kΩGo
- Moved the additional notes in the typical application diagram from the
picture to below the diagramGo
- Added a note to explain the differences between the decoupling
capacitorsGo
- Added a note to clarify the power-up sequence between VDD18 and
VDDIOGo
- Removed T0 and T2 since the order of VDD18 and VDDIO does not
matterGo
- Changed the pull-up resistor for PDB from 33-kΩ to
10-kΩGo