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ZHCSNJ7A April 2021 – February 2023 TDES954

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

RGZ|48
- MPQF123F

散熱焊盤機械數據 (封裝 | 引腳)

RGZ|48
- QFND014T

訂購信息

7.4.13.2 GPIO Output Pin Control

Individual GPIO output pin control is programmable through the GPIOx_PIN_CTL registers 0x10 to 0x16 (Table 7-35). To enable any of the GPIO as output, set bit 0 = 1 in the respective register 0x10 to 0x16 after clearing the corresponding input enable bit in register 0x0F (Table 7-34). The configuration register for each GPIO is listed in Table 7-7.

Figure 7-6 GPIOx Register Content (0x10 - 0x16)

7	6	5	4	3	2	1	0
GPIOX_OUTPUT_SEL[2:0]			GPIOX_OUT_SRC[2:0]			GPIOX_OUT_VAL	GPIOX_OUT_EN

Table 7-7 GPIOx Output Function Programming

GPIO OUTPUT FUNCTION	GPIOX OUTPUT SOURCE SELECT GPIOX_OUT_SRC[2:0]		GPIOX OUTPUT FUNCTION SELECT GPIOX_OUTPUT_SEL[2:0]	GPIOX OUTPUT VALUE (GPIOX_OUT_VAL)	GPIO OUTPUT ENABLE (GPIOX_OUT EN)
GPIO OUTPUT FUNCTION	VALUE	OUTPUT SIGNAL SOURCE	GPIOX OUTPUT FUNCTION SELECT GPIOX_OUTPUT_SEL[2:0]	GPIOX OUTPUT VALUE (GPIOX_OUT_VAL)	GPIO OUTPUT ENABLE (GPIOX_OUT EN)
GPIOX output disabled	X	No output. GPIO is Disabled or set to input mode	X	X	0
GPIOX linked to Forward channel received GPIO0 from RX Port 0 Serializer	000	RX Port 0	000	X	1
GPIOX linked to Forward channel received GPIO1 from RX Port 0 Serializer			001	X	1
GPIOX linked to Forward channel received GPIO2 from RX Port 0 Serializer			010	X	1
GPIOX linked to Forward channel received GPIO3 from RX Port 0 Serializer			011	X	1
RX Port 0 Lock indication			100	X	1
RX Port 0 Pass indication			101	X	1
RX Port 0 Frame Valid signal			110	X	1
RX Port 0 Line Valid signal			111	X	1
GPIOX linked to Forward channel received GPIO0 from RX Port 1 Serializer	001	RX Port 1	000	X	1
GPIOX linked to Forward channel received GPIO1 from RX Port 1 Serializer			001	X	1
GPIOX linked to Forward channel received GPIO2 from RX Port 1 Serializer			010	X	1
GPIOX linked to Forward channel received GPIO3 from RX Port 1 Serializer			011	X	1
RX Port 1 Lock indication			100	X	1
RX Port 1 Pass indication			101	X	1
RX Port 1 Frame Valid signal			110	X	1
RX Port 1 Line Valid signal			111	X	1
Reserved	010	Reserved	X	X	X
Set GPI0X = LOW value programmed by register	100	Device Status	000	0	1
Set GPIOX = HIGH value programmed by register			000	1	1
Logical OR of Lock indication from enabled RX ports			001	X	1
Logical AND of Lock indication from enabled RX ports			010	X	1
Logical AND of Pass indication from enabled RX ports			011	X	1
FrameSync signal (internal or external)			100	X	1
Device interrupt active high			101	X	1
Device interrupt active low			110	X	1
Reserved	100	Reserved	111	X	X
Pass (AND of selected RX port status)	101	CSI-2 Tx Port	000	X	1
Pass (OR of selected RX port status)			001	X	1
Frame Valid signal corresponding to video frame recovered at deserializer (Note) Insert cross reference			010	X	1
Line Valid signal corresponding to video frame recovered at deserializer (Note) Insert cross reference			011	X	1
RX Ports synchronized, RX Port 0 synchronized with RX Port 1			100	X	1
:CSI-2 TX Port Interrupt active high			101	X	1
Reserved	101	Reserved	110	X	X
Reserved	101	Reserved	111	X	X
Reserved	110	Reserved	X	X	X
Reserved	111	Reserved	X	X	X