ZHCSMU9A December 2020 – September 2021 TAS2764
PRODUCTION DATA
The TAS2764 can operate with both VBAT1S and PVDD as supplies or with only PVDD as supply. The table below shows different power supply modes of operation depending on the customer need.
| Supply Power Mode | Output Switching Mode | Supply Condition | Device Configurations | Use Case and Device Functionality | |
|---|---|---|---|---|---|
| PWR_MODE1 | Y Bridge High Power on VBAT1S | PVDD>VBAT1S | VBAT1S_MODE=0 BOP_SRC=0 CDS_MODE[1:0]=00 | VBAT1S is used to deliver output power based on level
and headroom configured. When audio signal crosses a programmed threshold Class-D
output is switched over PVDD. BOP source is VBAT1S. PVDD UVLO is disabled. SAR conversion done for VBAT1S, PVDD and temperature. |
|
| PWR_MODE2 | Y Bridge Low Power on VBAT1S | PVDD>VBAT1S+2.5V | VBAT1S_MODE=1 BOP_SRC=1CDS_MODE[1:0]=11 | PVDD is the only supply. VBAT1S is delivered by an
internal LDO and used to supply at signals close to idle channel levels.
When audio signal levels crosses -100dBFS (default), Class_D output switches to
PVDD. BOP source is PVDD. PVDD UVLO is enabled. SAR conversion done for PVDD and temperature. |
|
| PWR_MODE3 | Y Bridge High Power on VBAT1S | PVDD>VBAT1S | VBAT1S_MODE=0 BOP_SRC=1 CDS_MODE[1:0]=00 | VBAT1S is used to deliver output power based on level
and headroom configured. When audio signal crosses a programmed threshold Class-D
output is switched over PVDD. BOP source is PVDD. PVDD UVLO is enabled. SAR conversion done for PVDD and temperature. |
|
| PWR_MODE4 | PVDD | PVDD>VBAT1S+2.5V | VBAT1S_MODE=1 BOP_SRC=1CDS_MODE[1:0]=10 | Class-D power supplied by PVDD branch of Y bridge.
VBAT1S is delivered by an internal LDO. BOP source is PVDD. PVDD UVLO is enabled. SAR conversion done for PVDD and temperature. |
|
For PWR_MODE2 and PWR_MODE4, by default, the internal ADC samples only the PVDD pin in order to meet the stringent requirement on brownout latency. If the monitoring of VBAT1S pin is needed the register bit CONV_VBAT_PVDD_MODE should be set to high. The additional monitoring of VBAT1S will come at the cost of losing brownout latency.
If VBAT1S is generated by internal LDO, customer needs to ensure that PVDD supply level is at least 2.5V above the VBAT1S voltage generated internally. To enable voltage protection the UVLO of PVDD supply should be set above 7.3V by using register bits PVDD_UVLO[5:0]. This will ensure that, with an internally generated VBAT1S of 4.8V, PVDD supply is at least 2.5V higher than VBAT1S.