ZHCSMU9A December 2020 – September 2021 TAS2764
PRODUCTION DATA
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| tH(SBCLK) | SBCLK high period | 20 | ns | |||
| tL(SBCLK) | SBCLK low period | 20 | ns | |||
| tSU(FSYNC) | FSYNC setup time | 8 | ns | |||
| tHLD(FSYNC) | FSYNC hold time | 8 | ns | |||
| tSU(SDIN/ICC) | SDIN/ICC setup time | 8 | ns | |||
| tHLD(SDIN/ICC) | SDIN/ICC hold time | 8 | ns | |||
| td(SBCLK_SDOUT/ICC) | SBCLK to SDOUT/ICC delay | 50% of SBCLK to 50% of SDOUT/ICC, IOVDD=1.8V | 2.8 | 13 | ns | |
| 50% of SBCLK to 50% of SDOUT/ICC, IOVDD=1.2V | 3.6 | 17 | ||||
| tr(SBCLK) | SBCLK rise time | 10 % - 90 % Rise Time | 8 | ns | ||
| tf(SBCLK) | SBCLK fall time | 90 % - 10 % Fall Time | 8 | ns | ||
Figure 6-1 I2C
Timing Diagram
Figure 6-2 TDM and
ICC Timing Diagram