ZHCSMU9A December 2020 – September 2021 TAS2764
PRODUCTION DATA
The TAS2764 Class-D output uses a Y-Bridge configuration to improve efficiency during playback. The LVS (Section 8.4.2.5) is internally used to select between the PVDD and VBAT1S supplies. This feature is enabled by setting CDS_MODE[1:0] bits to 2'b00 when both PVDD and VBAT1S are supplied to the device. If not configured to Y-bridge mode the device will use only the selected supply for class-D output even if clipping would otherwise occur. The device can operate using only PVDD to supply class-D output. In this configuration the VBAT1S can be provided from external supply (register bit VBAT1S=0) or generated by an internal LDO (register bit VBAT1S=1). In this case CDS_MODE[1:0] bits should be set to 2'b10. The TAS2764 Y-Bridge with Low Power on VBAT1S can be used to switch to the VBAT1S rail only at very low power when close to idle. This will reduce the class-D output swing when near idle and limit the current requirements of the VBAT1S supply. Set the CDS_MODE[1:0] register to 2'b11 for this mode.
See Section 11.1 for details on programming the power modes.
The change to the class-D supply determined by the LVS (Section 8.4.2.5) can have a delay programed by CDS_DLY[1:0] register bits.
When in Y-Bridge mode, if the PVDD falls below (VBAT1S+2.5V) level the Y-bridge will stop switching between supplies and will remain on the PVDD supply.