ZHCSMU9A December 2020 – September 2021 TAS2764
PRODUCTION DATA
The TAS2764 operates using a TDM/I2S interface. Audio input and output are provided via the FSYNC, SBCLK, SDIN and SDOUT pins using formats including I2S, Left Justified and TDM. Configuration and status are provided via the SDA and SCL pins using the I2C protocol.
The table below illustrates how to configure the device for I2C address . The slave addresses are shown left shifted by one bit with the R/W bit set to 0 (i.e. {ADDR[6:0],1b0}). Resistors with tolerance better than 5% must be used for setting the address configuration.
| I2C SLAVE ADDRESS | 0x70 | 0x72 | 0x74 | 0x76 | 0x78 | 0x7A | 0x7C | 0x7E |
| ADDR PIN | Short to GND | 470 Ω to GND | 470 Ω to AVDD | 2.2k Ω to GND | 2.2k Ω to AVDD | 10 kΩ to GND | 10 kΩ to AVDD | Short to AVDD |
The TAS2764 has a global 7-bit I2C address 0x80. When enabled, the device will additionally respond to I2C commands at this address regardless of the ADDR pin settings. This is used to speed up device configuration when using multiple TAS2764 devices and programming similar settings across all devices. The I2C ACK / NACK cannot be used during the multi-device writes since multiple devices are responding to the I2C command. The I2C CRC function should be used to ensure each device properly received the I2C commands. At the completion of writing multiple devices using the global address, the CRC at I2C_CKSUM register should be checked on each device using the local address for a proper value. The global I2C address can be disabled using I2C_GBL_EN register bit. The I2C address is detected by sampling the ADDR pin when SDZ pin is released. Additionally, the address may be re-detected by setting I2C_AD_DET register bit high after power up and the ADDR pin will be re-sampled.