ZHCSRU7E november 2002 – march 2023 SN65HVD08 , SN75HVD08
PRODUCTION DATA
The differential receivers of the SNx5HVD08 family are “failsafe” to invalid bus states caused by:
In any of these cases, the differential receiver will output a failsafe logic High state so that the output of the receiver is not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds such that the “input indeterminate” range does not include zero volts differential.
In order to comply with the RS-422 and RS-485 standards, the receiver output must output a High when the differential input VID is more positive than +200 mV, and must output a Low when VID is more negative than -200 mV. The receiver parameters which determine the failsafe performance are VIT(+) and VIT(-).
As shown in the Electrical Characteristics table, differential signals more negative than -200 mV will always cause a Low receiver output, and differential signals more positive than -10 mV will always cause a High receiver output. Thus, when the differential input signal is close to zero, it is still above the maximum VIT(+) threshold of -10 mV, and the receiver output will be High.