ZHCSH29B April 2017 – December 2018 LP87524B-Q1 , LP87524J-Q1 , LP87524P-Q1
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Address: 0x2F
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| Reserved | GPIO3_OUT | GPIO2_OUT | GPIO1_OUT | ||||
| Bits | Field | Type | Default | Description |
|---|---|---|---|---|
| 7:3 | Reserved | R/W | 0x00 | |
| 2 | GPIO3_OUT | R/W | 1 * | Control for GPIO3 signal when configured to GPIO Output:
0 - Logic low level 1 - Logic high level |
| 1 | GPIO2_OUT | R/W | 1 * | Control for GPIO2 signal when configured to GPIO Output:
0 - Logic low level 1 - Logic high level |
| 0 | GPIO1_OUT | R/W | 0 | Control for GPIO1 signal when configured to GPIO Output:
0 - Logic low level 1 - Logic high level |