ZHCSH29B April 2017 – December 2018 LP87524B-Q1 , LP87524J-Q1 , LP87524P-Q1
PRODUCTION DATA.
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Address: 0x1B
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| Reserved | RESET_REG | ||||||
| Bits | Field | Type | Default | Description |
|---|---|---|---|---|
| 7:1 | Reserved | R/W | 0x00 | |
| 0 | RESET_REG | R/W | 0 | Latched status bit indicating that either start-up (NRST rising edge) is done, VANA supply voltage has been below undervoltage threshold level, or the host has requested a reset (SW_RESET bit in RESET register). The regulators have been disabled, and registers are reset to default values and the normal start-up procedure is done.
Write 1 to clear interrupt. |