JULIA无码中文一区,日本精品中文字幕在线播放,国产成人精品日本亚洲成熟

ZHCSK16A October 2017 – July 2019 LMK04228

PRODUCTION DATA.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

NKD|64
- MPQS032C

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

NKD|64
- QFND765

訂購信息

zhcsk16a_oa

7.5 Electrical Characteristics

(3.15 V < V_CC < 3.45 V, –40°C < T_A < 85°C. Typical values at V_CC = 3.3 V, T_A = 25°C, at the Recommended Operating Conditions and are not assured.)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
CURRENT CONSUMPTION
I_{CC_PD}	Power-down supply current				1	3	mA
I_{CC_CLKS}	Supply current⁽²⁾	14 LVDS clocks enabled PLL1 and PLL2 locked.			485		mA
CLKin0/0, CLKin1/1, AND CLKin2/2* INPUT CLOCK SPECIFICATIONS
f_CLKin	Clock input frequency			0.001		400	MHz
SLEW_CLKin	Clock input slew rate⁽³⁾	20% to 80%		0.15	0.5		V/ns
V_IDCLKin	Clock input differential input voltage⁽¹⁾ Figure 2	AC-coupled		0.125		1.55	\|V\|
V_SSCLKin	Clock input differential input voltage⁽¹⁾ Figure 2	AC-coupled		0.25		3.1	Vpp
V_CLKin	Clock input single-ended input voltage	AC-coupled to CLKinX; CLKinX* AC-coupled to Ground CLKinX_TYPE = 0 (Bipolar)		0.25		2.4	Vpp
V_CLKin	Clock input single-ended input voltage	AC-coupled to CLKinX; CLKinX* AC-coupled to Ground CLKinX_TYPE = 1 (MOS)		0.35		2.4	Vpp
V_{CLKinX-offset}\|	DC offset voltage between CLKinX/CLKinX* (CLKinX* – CLKinX)	Each pin AC-coupled, CLKin0/1/2 CLKinX_TYPE = 0 (Bipolar)			0		\|mV\|
	DC offset voltage between CLKinX/CLKinX* (CLKinX* – CLKinX)	Each pin AC-coupled, CLKin0/1 CLKinX_TYPE = 1 (MOS)			55
	DC offset voltage between CLKin2/CLKin2* (CLKin2* – CLKin2)	Each pin AC-coupled CLKinX_TYPE = 1 (MOS)			20
V_CLKin- V_IH	High input voltage	DC-coupled to CLKinX; CLKinX* AC-coupled to Ground CLKinX_TYPE = 1 (MOS)		2		V_CC	V
V_CLKin- V_IL	Low input voltage			0		0.4	V
PLL1 SPECIFICATIONS
f_PD1	PLL1 phase detector frequency					40	MHz
I_CPout1SOURCE	PLL1 charge pump source current⁽⁴⁾	V_CPout1 = V_CC/2, PLL1_CP_GAIN = 0			50		µA
		V_CPout1 = V_CC/2, PLL1_CP_GAIN = 1			150
		V_CPout1 = V_CC/2, PLL1_CP_GAIN = 2			250
		…			…
		V_CPout1 = V_CC/2, PLL1_CP_GAIN = 14			1450
		V_CPout1 = V_CC/2, PLL1_CP_GAIN = 15			1550
I_CPout1SINK	PLL1 charge pump sink current⁽⁴⁾	V_CPout1=V_CC/2, PLL1_CP_GAIN = 0			–50		µA
		V_CPout1=V_CC/2, PLL1_CP_GAIN = 1			–150
		V_CPout1=V_CC/2, PLL1_CP_GAIN = 2			–250
		…			…
		V_CPout1=V_CC/2, PLL1_CP_GAIN = 14			–1450
		V_CPout1=V_CC/2, PLL1_CP_GAIN = 15			–1550
I_CPout1%MIS	Charge pump sink / source mismatch	V_CPout1 = V_CC/2, T = 25 °C			1%	10%
I_CPout1V_TUNE	Magnitude of charge pump current variation vs. charge pump voltage	0.5 V < V_CPout1 < V_CC – 0.5 V T_A = 25°C			4%
I_CPout1%TEMP	Charge pump current vs. temperature variation				4%
I_CPout1 TRI	Charge pump TRI-STATE leakage current	0.5 V < V_CPout < V_CC – 0.5 V				5	nA
PN10kHz	PLL 1/f noise at 10-kHz offset. Normalized to 1-GHz output frequency	PLL1_CP_GAIN = 350 µA			–117		dBc/Hz
PN10kHz		PLL1_CP_GAIN = 1550 µA			–118		dBc/Hz
PN1Hz	Normalized phase noise contribution	PLL1_CP_GAIN = 350 µA			–221.5		dBc/Hz
PN1Hz	Normalized phase noise contribution	PLL1_CP_GAIN = 1550 µA			–223		dBc/Hz
PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS
f_OSCin	PLL2 reference input⁽⁶⁾					500	MHz
SLEW_OSCin	PLL2 reference clock minimum slew rate on OSCin ⁽³⁾	20% to 80%		0.15	0.5		V/ns
V_OSCin	Input voltage for OSCin or OSCin*	AC-coupled; single-ended (Unused pin AC-coupled to GND)		0.2		2.4	Vpp
V_IDOSCin	Differential voltage swing See Figure 2	AC-coupled		0.2		1.55	\|V\|
V_SSOSCin	Differential voltage swing See Figure 2	AC-coupled		0.4		3.1	Vpp
\|V_OSCin-offset\|	DC offset voltage between OSCin/OSCin* (OSCinX* - OSCinX)	Each pin AC-coupled			20		\|mV\|
f_{doubler_max}	Doubler input frequency ⁽⁵⁾	EN_PLL2_REF_2X = 1⁽⁷⁾; OSCin duty cycle 40% to 60%				155	MHz
CRYSTAL OSCILLATOR MODE SPECIFICATIONS
F_XTAL	Crystal frequency range	Fundamental mode crystal ESR = 200 Ω (10 to 30 MHz) ESR = 125 Ω (30 to 40 MHz)		10		40	MHz
C_IN	Input capacitance of OSCin port	–40°C to +85°C			1		pF
PLL2 PHASE DETECTOR AND CHARGE PUMP SPECIFICATIONS
f_PD2	Phase detector frequency ⁽⁵⁾					155	MHz
I_CPoutSOURCE	PLL2 charge pump source current ⁽⁴⁾	V_CPout2=V_CC/2, PLL2_CP_GAIN = 0			100		µA
		V_CPout2=V_CC/2, PLL2_CP_GAIN = 1			400
		V_CPout2=V_CC/2, PLL2_CP_GAIN = 2			1600
I_CPoutSINK	PLL2 charge pump sink current ⁽⁴⁾	V_CPout2=V_CC/2, PLL2_CP_GAIN = 0			–100		µA
		V_CPout2=V_CC/2, PLL2_CP_GAIN = 1			–400
		V_CPout2=V_CC/2, PLL2_CP_GAIN = 2			–1600
I_CPout2%MIS	Charge pump sink/source mismatch	V_CPout2=V_CC/2, T_A = 25°C			1%	10%
I_CPout2V_TUNE	Magnitude of charge pump current vs. charge pump voltage variation	0.5 V < V_CPout2 < V_CC – 0.5 V T_A = 25°C			4%
I_CPout2%TEMP	Charge pump current vs. temperature variation				4%
I_CPout2TRI	Charge pump leakage	0.5 V < V_CPout2 < V_CC – 0.5 V				10	nA
PN10kHz	PLL 1/f noise at 10-kHz offset⁽⁸⁾. Normalized to 1-GHz output frequency	PLL2_CP_GAIN = 1600 µA			–120		dBc/Hz
PN1Hz	Normalized phase noise contribution⁽⁹⁾	PLL2_CP_GAIN = 400 µA			–222.5		dBc/Hz
PN1Hz	Normalized phase noise contribution⁽⁹⁾	PLL2_CP_GAIN = 1600 µA			–224		dBc/Hz
INTERNAL VCO SPECIFICATIONS
f_VCO	LMK04228 VCO tuning range	VCO0		2370		2630	MHz
f_VCO	LMK04228 VCO tuning range	VCO1		2920		3080	MHz
K_VCO	LMK04228 fine tuning sensitivity	LMK04228 VCO0 at 2370 MHz⁽¹⁰⁾			17		MHz/V
		LMK04228 VCO0 at 2630 MHz⁽¹⁰⁾			27
		LMK04228 VCO1 at 2920 MHz⁽¹⁰⁾			17
		LMK04228 VCO1 at 3080 MHz⁽¹⁰⁾			23
\|ΔT_CL\|	Allowable temperature drift for continuous lock⁽¹¹⁾	After programming for lock, no changes to output configuration are permitted to assure continuous lock				125	°C
NOISE FLOOR
L(f)_CLKout	LMK04228, VCO0, noise floor 20-MHz offset⁽¹²⁾	245.76 MHz	LVDS		–156.3		dBc/Hz
			LVPECL16 with 240 Ω		–161.6
			LVPECL20 with 240 Ω		–162.5
L(f)_CLKout	LMK04228, VCO1, noise floor 20-MHz offset⁽¹²⁾	245.76 MHz	LVDS		–155.7		dBc/Hz
			LVPECL16 with 240 Ω		–160.3
			LVPECL20 with 240 Ω		–161.1
CLKout CLOSED-LOOP PHASE NOISE SPECIFICATIONS A COMMERCIAL QUALITY VCXO⁽¹⁵⁾
L(f)_CLKout	LMK04228 VCO0 SSB phase noise⁽¹²⁾ 245.76 MHz	Offset = 1 kHz			–115.2		dBc/Hz
		Offset = 10 kHz			–126.5
		Offset = 100 kHz			–128.3
		Offset = 1 MHz			–150.0
		Offset = 10 MHz	LVDS		–157.9
		Offset = 10 MHz	LVPECL20 with 240 Ω		–163.1
L(f)_CLKout	LMK04228 VCO1 SSB phase noise⁽¹²⁾ 245.76 MHz	Offset = 1 kHz			–115.1		dBc/Hz
		Offset = 10 kHz			–126.3
		Offset = 100 kHz			–127.5
		Offset = 1 MHz			–154.4
		Offset = 10 MHz	LVDS		–157.9
		Offset = 10 MHz	LVPECL20 with 240 Ω		–162.3
CLKout CLOSED-LOOP JITTER SPECIFICATIONS A COMMERCIAL QUALITY VCXO⁽¹⁵⁾
J_CLKout	LMK04228, VCO0 f_CLKout = 245.76 MHz Integrated RMS jitter ⁽¹²⁾	LVDS, BW = 100 Hz to 20 MHz			256		fs rms
		LVDS, BW = 12 kHz to 20 MHz			183
		LVPECL20 /w 240 Ω, BW = 100 Hz to 20 MHz			254
		LVPECL20 /w 240 Ω, BW = 12 kHz to 20 MHz			176
	LMK04228, VCO1 f_CLKout = 245.76 MHz Integrated RMS jitter ⁽¹²⁾	LVDS, BW = 100 Hz to 20 MHz			246
		LVDS, BW = 12 kHz to 20 MHz			162
		LVPECL16 with 240 Ω, BW = 100 Hz to 20 MHz			245
		LVPECL20 with 240 Ω, BW = 12 kHz to 20 MHz			156
DEFAULT POWER ON RESET CLOCK OUTPUT FREQUENCY
f_{CLKout-startup}	Default output clock frequency at device power on ⁽¹⁶⁾⁽¹⁷⁾	LMK04228			315		MHz
f_OSCout	OSCout frequency	See⁽⁵⁾				500	MHz
CLOCK SKEW AND DELAY
\|T_SKEW\|	DCLKoutX to SDCLKoutY F_CLK = 245.76 MHz, R_L= 100 Ω AC-coupled⁽¹³⁾	Same pair, same format ⁽¹⁴⁾ SDCLKoutY_MUX = 0 (device clock)				25	\|ps\|
\|T_SKEW\|	Maximum DCLKoutX or SDCLKoutY to DCLKoutX or SDCLKoutY F_CLK = 245.76 MHz, R_L= 100 Ω AC-coupled	Any pair, same format ⁽¹⁴⁾ SDCLKoutY_MUX = 0 (device clock)			50		\|ps\|
ts_JESD204B	SYSREF to device clock setup time base reference. See SYSREF to Device Clock Alignment to adjust SYSREF to device clock setup time as required.	SDCLKoutY_MUX = 1 (SYSREF) SYSREF_DIV = 30 SYSREF_DDLY = 8 (global) SDCLKoutY_DDLY = 1 (2 cycles, local) DCLKoutX_MUX = 1 (Div+DCC+HS) DCLKoutX_DIV = 30 DCLKoutX_DDLY_CNTH = 7 DCLKoutX_DDLY_CNTL = 6 DCLKoutX_HS = 0 SDCLKoutY_HS = 0			–80		ps
t_PDCLKin0_ SDCLKout1	Propagation delay from CLKin0 to SDCLKout1	CLKin0_OUT_MUX = 0 (SYSREF Mux) SYSREF_CLKin0_MUX = 1 (CLKin0) SDCLKout1_PD = 0 SDCLKout1_DDLY = 0 (Bypass) SDCLKout1_MUX = 1 (SR) EN_SYNC = 1 LVPECL16 with 240 Ω			0.65		ns
f_ADLYmax	Maximum analog delay frequency	DCLKoutX_MUX = 4		1250			MHz
LVDS CLOCK OUTPUTS (DCLKoutX, SDCLKoutY, AND OSCout)
V_OD	Differential output voltage	T = 25°C, DC measurement AC-coupled to receiver input R_L = 100-Ω differential termination			395		\|mV\|
ΔV_OD	Change in magnitude of V_OD for complementary output states			–60		60	mV
V_OS	Output offset voltage			1.125	1.25	1.375	V
ΔV_OS	Change in V_OS for complementary output states					35	\|mV\|
T_R / T_F	Output rise time	20% to 80%, R_L = 100 Ω, 245.76 MHz			180		ps
T_R / T_F	Output fall time	80% to 20%, R_L = 100 Ω			180		ps
I_SA I_SB	Output short-circuit current - single-ended	Single-ended output shorted to GND T = 25°C		–24		24	mA
I_SAB	Output short-circuit current - differential	Complementary outputs tied together		–12		12	mA
LVPECL CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY)
T_R / T_F	20% to 80% output rise	R_L = 100 Ω, emitter resistors = 240 Ω to GND DCLKoutX_TYPE = 4 or 5 (1600 or 2000 mVpp)			150		ps
T_R / T_F	80% to 20% output fall time				150		ps
1600-mVpp LVPECL CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY)
V_OH	Output high voltage	DC Measurement Termination = 50 Ω to V_CC – 2 V			V_CC – 1.04		V
V_OL	Output low voltage				V_CC – 1.80		V
V_OD	Output voltage See Figure 3				760		\|mV\|
2000-mVpp LVPECL CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY)
V_OH	Output high voltage	DC Measurement Termination = 50 Ω to V_CC – 2.3 V			V_CC – 1.09		V
V_OL	Output low voltage				V_CC – 2.05		V
V_OD	Output voltage See Figure 3				960		\|mV\|
LVCMOS CLOCK OUTPUTS (OSCout)
f_CLKout	Maximum frequency⁽¹⁸⁾	5-pF Load		250			MHz
V_OH	Output high voltage	1-mA Load		V_CC – 0.1			V
V_OL	Output low voltage	1-mA Load				0.1	V
I_OH	Output high current (source)	V_CC = 3.3 V, V_O = 1.65 V			28		mA
I_OL	Output low current (sink)	V_CC = 3.3 V, V_O = 1.65 V			28		mA
DUTY_CLK	Output duty cycle⁽²⁰⁾	V_CC/2 to V_CC/2, F_CLK = 100 MHz, T = 25°C			50%
T_R	Output rise time	20% to 80%, R_L = 50 Ω, C_L = 5 pF			400		ps
T_F	Output fall time	80% to 20%, R_L = 50 Ω, C_L = 5 pF			400		ps
DIGITAL OUTPUTS (CLKin_SELX, Status_LDX, AND RESET/GPO)
V_OH	High-level output voltage	I_OH = –500 µA CLKin_SELX_TYPE = 3 or 4 Status_LDX_TYPE = 3 or 4 RESET_TYPE = 3 or 4		V_CC – 0.4			V
V_OL	Low-level output voltage	I_OL = 500 µA CLKin_SELX_TYPE = 3, 4, or 6 Status_LDX_TYPE = 3, 4, or 6 RESET_TYPE = 3, 4, or 6				0.4	V
DIGITAL OUTPUT (SDIO)
V_OH	High-level output voltage	I_OH = –500 µA ; during SPI read. SDIO_RDBK_TYPE = 0		V_CC – 0.4			V
V_OL	Low-level output voltage	I_OL = 500 µA ; during SPI read. SDIO_RDBK_TYPE = 0 or 1				0.4	V
DIGITAL INPUTS (CLKinX_SEL, RESET/GPO, SYNC, SCK, SDIO, OR CS*)
V_IH	High-level input voltage			1.2		V_CC	V
V_IL	Low-level input voltage					0.4	V
DIGITAL INPUTS (CLKinX_SEL)
I_IH	High-level input current V_IH = V_CC	CLKin_SELX_TYPE = 0, (high impedance)		–5		5	µA
		CLKin_SELX_TYPE = 1 (pullup)		–5		5
		CLKin_SELX_TYPE = 2 (pulldown)		10		80
I_IL	Low-level input current V_IL = 0 V	CLKin_SELX_TYPE = 0, (High Impedance)		–5		5	µA
		CLKin_SELX_TYPE = 1 (pullup)		–40		–5
		CLKin_SELX_TYPE = 2 (pulldown)		–5		5
DIGITAL INPUT (RESET/GPO)
I_IH	High-level input current V_IH = V_CC	RESET_TYPE = 2 (pulldown)		10		80	µA
I_IL	Low-level input current V_IL = 0 V	RESET_TYPE = 0 (high impedance)		–5		5	µA
		RESET_TYPE = 1 (pullup)		–40		-5
		RESET_TYPE = 2 (pulldown)		–5		5
DIGITAL INPUTS (SYNC)
I_IH	High-level input current	V_IH = V_CC				25	µA
I_IL	Low-level input current	V_IL = 0 V		–5		5
DIGITAL INPUTS (SCK, SDIO, CS*)
I_IH	High-level input current	V_IH = V_CC		–5		5	µA
I_IL	Low-level input current	V_IL = 0		–5		5	µA
DIGITAL INPUT TIMING
t_HIGH		RESET pin held high for device reset		25			ns

(1) See Differential Voltage Measurement Terminology for definition of V_ID and V_OD voltages.

(2) See applications section Power Supply Recommendations for specific part configuration and how to calculate the I_CC for a specific design.

(3) To meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to their common-mode noise rejection. However, TI also recommends using the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs.

(4) This parameter is programmable

(5) Assured by characterization. ATE tested at 122.88 MHz.

(6) F_OSCin maximum frequency assured by characterization. Production tested at 122.88 MHz.

(7) The EN_PLL2_REF_2X bit enables/disables a frequency doubler mode for the PLL2 OSCin path.

(8) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, L_{PLL_flicker}(f), which is dominant close to the carrier. Flicker noise has a 10 dB/decade slope. PN10kHz is normalized to a 10-kHz offset and a 1-GHz carrier frequency. PN10kHz = L_{PLL_flicker}(10 kHz) – 20log(Fout / 1 GHz), where L_{PLL_flicker}(f) is the single-side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure L_{PLL_flicker}(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). L_{PLL_flicker}(f) can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of L_{PLL_flicker}(f) and L_{PLL_flat}(f).

(9) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, L_{PLL_flat}(f), is defined as: PN1HZ=L_{PLL_flat}(f) – 20log(N) – 10log(f_PDX). L_{PLL_flat}(f) is the single-side band phase noise measured at an offset frequency, f, in a 1-Hz bandwidth and f_PDX is the phase detector frequency of the synthesizer. L_{PLL_flat}(f) contributes to the total noise, L(f).

(10) For frequencies in between, linearly interpolate to compute the typical Kvco

(11) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the 0x168 register was last programmed with PLL2_FCAL_DIS = 0, and still have the part stay in lock. The action of programming the 0x168 register, even to the same value, activates a frequency calibration routine. This implies the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the appropriate register to ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the frequency range of –40°C to 85°C without violating specifications.

(12) Data collected using MACOM H-183-4 balun. Loop filter is C1 = 82 pF, C2 = 2.2 nF, R2 = 1800 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω, PLL1_CP = 650 µA, PLL2_CP = 1600 µA. VCO0 loop filter bandwidth = 176 kHz, phase margin = 67 degrees. VCO1 Loop filter loop bandwidth = 169 kHz, phase margin = 66 degrees. CLKoutX_Y_IDL = 1, CLKoutX_Y_ODL = 0.

(13) Equal loading and identical clock output configuration on each clock output is required for specification to be valid. Specification not valid for delay mode.

(14) LVPECL uses 120-Ω emitter resistor, LVDS uses 560-Ω shunt.

(15) VCXO used is a 30.72 MHz (TXC Bex05).

(16) OSCout will oscillate at start-up at the frequency of the VCXO attached to OSCin port.

(17) Default outputs on DCLKout4, DCLKout6, DCLKout8, DCLKout10 and OSCout.

(18) Assured by characterization. ATE tested to 10 MHz.

(19) 20 MHz

(20) Assumes OSCin has 50% input duty cycle.