ZHCSK16A October 2017 – July 2019 LMK04228
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1
Overview
- 9.1.1 Jitter Cleaning
- 9.1.2 JEDEC JESD204B Support
- 9.1.3 Three PLL1 Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*, and CLKin2/CLKin2*)
- 9.1.4 VCXO- and Crystal-Buffered Output
- 9.1.5 Frequency Holdover
- 9.1.6 PLL2 Integrated Loop Filter Poles
- 9.1.7 Internal VCOs
- 9.1.8 Clock Distribution
- 9.1.9 Status Pins
- 9.2 Functional Block Diagrams
- 9.3 Feature Description
- 9.4 Programming
- 9.5
Register Maps
- 9.5.1 Register Map for Device Programming
- 9.5.2
Device Register Descriptions
- 9.5.2.1 System Functions
- 9.5.2.2
(0x100 - 0x138) Device Clock and SYSREF Clock Output Controls
- 9.5.2.2.1 CLKoutX_Y_ODL, CLKoutX_Y_IDL, DCLKoutX_DIV
- 9.5.2.2.2 DCLKoutX_DDLY_CNTH, DCLKoutX_DDLY_CNTL
- 9.5.2.2.3 DCLKoutX_ADLY, DCLKoutX_ADLY_MUX, DCLKout_MUX
- 9.5.2.2.4 DCLKoutX_HS, SDCLKoutY_MUX, SDCLKoutY_DDLY, SDCLKoutY_HS
- 9.5.2.2.5 SDCLKoutY_ADLY_EN, SDCLKoutY_ADLY
- 9.5.2.2.6 DCLKoutX_DDLY_PD, DCLKout_ADLY_PD, DCLKoutX_Y_PD, SDCLKoutY_DIS_MODE, SDCLKoutY_PD
- 9.5.2.2.7 SDCLKoutY_POL, SDCLKoutY_FMT, DCLKoutX_POL, DCLKoutX_FMT
- 9.5.2.3
SYSREF, SYNC, and Device Config
- 9.5.2.3.1 VCO_MUX, OSCout_FMT
- 9.5.2.3.2 SYSREF_CLKin0_MUX, SYSREF_MUX
- 9.5.2.3.3 SYSREF_DIV[12:8], SYSREF_DIV[7:0]
- 9.5.2.3.4 SYSREF_DDLY[12:8], SYSREF_DDLY[7:0]
- 9.5.2.3.5 SYSREF_PULSE_CNT
- 9.5.2.3.6 PLL1_PD, VCO_LDO_PD, VCO_PD, OSCin_PD, SYSREF_GBL_PD, SYSREF_PD, SYSREF_DDLY_PD, SYSREF_PLSR_PD
- 9.5.2.3.7 SYSREF_CLR, SYNC_1SHOT_EN, SYNC_POL, SYNC_EN, SYNC_PLL2_DLD, SYNC_PLL1_DLD, SYNC_MODE
- 9.5.2.3.8 SYNC_DISSYSREF, SYNC_DISX
- 9.5.2.3.9 Fixed Register
- 9.5.2.4 (0x146 - 0x149) CLKin Control
- 9.5.2.5 RESET_MUX, RESET_TYPE
- 9.5.2.6
(0x14B - 0x152) Holdover
- 9.5.2.6.1 LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8]
- 9.5.2.6.2 MAN_DAC[9:8], MAN_DAC[7:0]
- 9.5.2.6.3 DAC_TRIP_LOW
- 9.5.2.6.4 DAC_CLK_MULT, DAC_TRIP_HIGH
- 9.5.2.6.5 DAC_CLK_CNTR
- 9.5.2.6.6 CLKin_OVERRIDE, HOLDOVER_PLL1_DET, HOLDOVER_LOS_DET, HOLDOVER_VTUNE_DET, HOLDOVER_HITLESS_SWITCH, HOLDOVER_EN
- 9.5.2.6.7 HOLDOVER_DLD_CNT[13:8], HOLDOVER_DLD_CNT[7:0]
- 9.5.2.7 (0x153 - 0x15F) PLL1 Configuration
- 9.5.2.8
(0x160 - 0x16E) PLL2 Configuration
- 9.5.2.8.1 PLL2_R[4:0]
- 9.5.2.8.2 PLL2_P, OSCin_FREQ, PLL2_XTAL_EN, PLL2_REF_2X_EN
- 9.5.2.8.3 PLL2_FCAL_DIS
- 9.5.2.8.4 PLL2_N
- 9.5.2.8.5 PLL2_WND_SIZE, PLL2_CP_GAIN, PLL2_CP_POL, PLL2_CP_TRI
- 9.5.2.8.6 SYSREF_REQ_EN, PLL2_DLD_CNT
- 9.5.2.8.7 PLL2_LF_R4, PLL2_LF_R3
- 9.5.2.8.8 PLL2_LF_C4, PLL2_LF_C3
- 9.5.2.8.9 PLL2_LD_MUX, PLL2_LD_TYPE
- 9.5.2.9
(0x16F - 0x1FFF) Misc Registers
- 9.5.2.9.1 Fixed Register
- 9.5.2.9.2 Fixed Register
- 9.5.2.9.3 PLL2_PRE_PD, PLL2_PD
- 9.5.2.9.4 OPT_REG_1
- 9.5.2.9.5 OPT_REG_2
- 9.5.2.9.6 RB_PLL1_LD_LOST, RB_PLL1_LD, CLR_PLL1_LD_LOST
- 9.5.2.9.7 RB_PLL2_LD_LOST, RB_PLL2_LD, CLR_PLL2_LD_LOST
- 9.5.2.9.8 RB_DAC_VALUE(MSB), RB_CLKinX_SEL, RB_CLKinX_LOS
- 9.5.2.9.9 RB_DAC_VALUE
- 9.5.2.9.10 RB_HOLDOVER
- 9.5.2.9.11 SPI_LOCK
- 9.1
Overview
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13器件和文檔支持
- 14機械、封裝和可訂購信息
9.3.3.1.1 Fixed Digital Delay Example
Assuming the device already has the following initial configurations, and the application should delay DCLKout2 by one VCO cycle compared to DCLKout0.
- VCO frequency = 2949.12 MHz
- DCLKout0 = 368.64 MHz (DCLKout0_DIV = 8)
- DCLKout2 = 368.64 MHz (DCLKout2_DIV = 8)
The following steps should be followed
- Set DCLKout0_DDLY_CNTH = 4 and DCLKout2_DDLY_CNTH = 4. First part of delay for each clock.
- Set DCLKout0_DDLY_CNTL = 4 and DCLKout2_DDLY_CNTL = 5. Second part of delay for each clock.
- Set DCLKout2_DDLY_PD = 0 and DCLKout2_DDLY_PD = 0. Power up the digital delay circuit.
- Set SYNC_DIS0 = 0 and SYNC_DIS2 = 0. Allow the output to be synchronized.
- Perform SYNC by asserting, then unasserting SYNC. Either by using SYNC_POL bit or the SYNC pin.
- Power down DCLKout2_DDLY_PD = 0 and/or DCLKout2_DDLY_PD = 1 to save power now that the SYNC is complete.
- Set SYNC_DIS0 = 1 and SYNC_DIS2 = 1 to prevent the output from being synchronized; this step is very important for steady-state operation when using JESD204B.
Figure 7. Fixed Digital Delay Example Table 4 shows the recommended DCLKoutX_DDLY_CNTH and DCLKoutX_DDLY_CNTL alternate divide setting for delay by one VCO cycle. The clock will output high during the DCLKoutX_DDLY_CNTH time to permit a continuous output clock. The clock output will be low during the DCLKoutX_DDLY_CNTL time.
Table 4. Recommended DCLKoutX_DDLY_CNTH/_CNTL Values for Delay by One VCO Cycle
| CLOCK DIVIDER | _CNTH | _CNTL | CLOCK DIVIDER | _CNTH | _CNTL | |
|---|---|---|---|---|---|---|
| 2 | 2 | 3 | 17 | 9 | 9 | |
| 3 | 3 | 4 | 18 | 9 | 10 | |
| 4 | 2 | 3 | 19 | 10 | 10 | |
| 5 | 3 | 3 | 20 | 10 | 11 | |
| 6 | 3 | 4 | 21 | 11 | 11 | |
| 7 | 4 | 4 | 22 | 11 | 12 | |
| 8 | 4 | 5 | 23 | 12 | 12 | |
| 9 | 5 | 5 | 24 | 12 | 13 | |
| 10 | 5 | 6 | 25 | 13 | 13 | |
| 11 | 6 | 6 | 26 | 13 | 14 | |
| 12 | 6 | 7 | 27 | 14 | 14 | |
| 13 | 7 | 7 | 28 | 14 | 15 | |
| 14 | 7 | 8 | 29 | 15 | 15 | |
| 15 | 8 | 8 | 30 | 15 | 16(1) | |
| 16 | 8 | 9 | 31 | 16(1) | 16(1) |
(1) To achieve _CNTH/_CNTL value of 16, 0 must be programmed into the _CNTH/_CNTL field.