ZHCSK16A October 2017 – July 2019 LMK04228
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1
Overview
- 9.1.1 Jitter Cleaning
- 9.1.2 JEDEC JESD204B Support
- 9.1.3 Three PLL1 Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*, and CLKin2/CLKin2*)
- 9.1.4 VCXO- and Crystal-Buffered Output
- 9.1.5 Frequency Holdover
- 9.1.6 PLL2 Integrated Loop Filter Poles
- 9.1.7 Internal VCOs
- 9.1.8 Clock Distribution
- 9.1.9 Status Pins
- 9.2 Functional Block Diagrams
- 9.3 Feature Description
- 9.4 Programming
- 9.5
Register Maps
- 9.5.1 Register Map for Device Programming
- 9.5.2
Device Register Descriptions
- 9.5.2.1 System Functions
- 9.5.2.2
(0x100 - 0x138) Device Clock and SYSREF Clock Output Controls
- 9.5.2.2.1 CLKoutX_Y_ODL, CLKoutX_Y_IDL, DCLKoutX_DIV
- 9.5.2.2.2 DCLKoutX_DDLY_CNTH, DCLKoutX_DDLY_CNTL
- 9.5.2.2.3 DCLKoutX_ADLY, DCLKoutX_ADLY_MUX, DCLKout_MUX
- 9.5.2.2.4 DCLKoutX_HS, SDCLKoutY_MUX, SDCLKoutY_DDLY, SDCLKoutY_HS
- 9.5.2.2.5 SDCLKoutY_ADLY_EN, SDCLKoutY_ADLY
- 9.5.2.2.6 DCLKoutX_DDLY_PD, DCLKout_ADLY_PD, DCLKoutX_Y_PD, SDCLKoutY_DIS_MODE, SDCLKoutY_PD
- 9.5.2.2.7 SDCLKoutY_POL, SDCLKoutY_FMT, DCLKoutX_POL, DCLKoutX_FMT
- 9.5.2.3
SYSREF, SYNC, and Device Config
- 9.5.2.3.1 VCO_MUX, OSCout_FMT
- 9.5.2.3.2 SYSREF_CLKin0_MUX, SYSREF_MUX
- 9.5.2.3.3 SYSREF_DIV[12:8], SYSREF_DIV[7:0]
- 9.5.2.3.4 SYSREF_DDLY[12:8], SYSREF_DDLY[7:0]
- 9.5.2.3.5 SYSREF_PULSE_CNT
- 9.5.2.3.6 PLL1_PD, VCO_LDO_PD, VCO_PD, OSCin_PD, SYSREF_GBL_PD, SYSREF_PD, SYSREF_DDLY_PD, SYSREF_PLSR_PD
- 9.5.2.3.7 SYSREF_CLR, SYNC_1SHOT_EN, SYNC_POL, SYNC_EN, SYNC_PLL2_DLD, SYNC_PLL1_DLD, SYNC_MODE
- 9.5.2.3.8 SYNC_DISSYSREF, SYNC_DISX
- 9.5.2.3.9 Fixed Register
- 9.5.2.4 (0x146 - 0x149) CLKin Control
- 9.5.2.5 RESET_MUX, RESET_TYPE
- 9.5.2.6
(0x14B - 0x152) Holdover
- 9.5.2.6.1 LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8]
- 9.5.2.6.2 MAN_DAC[9:8], MAN_DAC[7:0]
- 9.5.2.6.3 DAC_TRIP_LOW
- 9.5.2.6.4 DAC_CLK_MULT, DAC_TRIP_HIGH
- 9.5.2.6.5 DAC_CLK_CNTR
- 9.5.2.6.6 CLKin_OVERRIDE, HOLDOVER_PLL1_DET, HOLDOVER_LOS_DET, HOLDOVER_VTUNE_DET, HOLDOVER_HITLESS_SWITCH, HOLDOVER_EN
- 9.5.2.6.7 HOLDOVER_DLD_CNT[13:8], HOLDOVER_DLD_CNT[7:0]
- 9.5.2.7 (0x153 - 0x15F) PLL1 Configuration
- 9.5.2.8
(0x160 - 0x16E) PLL2 Configuration
- 9.5.2.8.1 PLL2_R[4:0]
- 9.5.2.8.2 PLL2_P, OSCin_FREQ, PLL2_XTAL_EN, PLL2_REF_2X_EN
- 9.5.2.8.3 PLL2_FCAL_DIS
- 9.5.2.8.4 PLL2_N
- 9.5.2.8.5 PLL2_WND_SIZE, PLL2_CP_GAIN, PLL2_CP_POL, PLL2_CP_TRI
- 9.5.2.8.6 SYSREF_REQ_EN, PLL2_DLD_CNT
- 9.5.2.8.7 PLL2_LF_R4, PLL2_LF_R3
- 9.5.2.8.8 PLL2_LF_C4, PLL2_LF_C3
- 9.5.2.8.9 PLL2_LD_MUX, PLL2_LD_TYPE
- 9.5.2.9
(0x16F - 0x1FFF) Misc Registers
- 9.5.2.9.1 Fixed Register
- 9.5.2.9.2 Fixed Register
- 9.5.2.9.3 PLL2_PRE_PD, PLL2_PD
- 9.5.2.9.4 OPT_REG_1
- 9.5.2.9.5 OPT_REG_2
- 9.5.2.9.6 RB_PLL1_LD_LOST, RB_PLL1_LD, CLR_PLL1_LD_LOST
- 9.5.2.9.7 RB_PLL2_LD_LOST, RB_PLL2_LD, CLR_PLL2_LD_LOST
- 9.5.2.9.8 RB_DAC_VALUE(MSB), RB_CLKinX_SEL, RB_CLKinX_LOS
- 9.5.2.9.9 RB_DAC_VALUE
- 9.5.2.9.10 RB_HOLDOVER
- 9.5.2.9.11 SPI_LOCK
- 9.1
Overview
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13器件和文檔支持
- 14機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- NKD|64
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- NKD|64
訂購信息
9.3.6 Digital Lock Detect
Both PLL1 and PLL2 support digital lock detect. Digital lock detect compares the phase between the reference path (R) and the feedback path (N) of the PLL. When the time error (and therefore the phase error) between the two signals is less than a window size (ε) specified by PLL1_WND_SIZE and PLL2_WND_SIZE, a lock detect count increments. When the lock detect count reaches a user specified value, PLL1_DLD_CNT or PLL2_DLD_CNT, lock detect is asserted true. Once digital lock detect is true, a single phase comparison outside the specified window will cause digital lock detect to be asserted false. This is illustrated in Figure 8.
Figure 8. Digital Lock Detect Flowchart This incremental lock detect count feature functions as a digital filter to ensure that lock detect isn't asserted for only a brief time when the phases of R and N are within the specified tolerance for only a brief time during initial phase lock.
See Digital Lock Detect Frequency Accuracy for more detailed information on programming the registers to achieve a specified frequency accuracy in ppm with lock detect.
The digital lock detect signal can be monitored on the Status_LD1 or Status_LD2 pin. The pin may be programmed to output the status of lock detect for PLL1, PLL2, or both PLL1 and PLL2.
NOTE
In cases where the period of the phase detector frequency approaches the value of the default PLL1_WND_SIZE increment (40 ns), the lock detect circuit will not function with the default value of PLL1_WND_SIZE. For phase detector frequencies at or above 25 MHz, TI recommends setting PLL1_WND_SIZE to 0x02 (19 ns) or a smaller value.