ZHCSK16A October 2017 – July 2019 LMK04228
PRODUCTION DATA.
The device clocks include both a analog and digital delay for phase adjustment of the clock outputs.
The analog delay allows a nominal 25-ps step size and range from 0 to 575 ps of granular delay. Enabling the device clock analog delay adds a nominal 500-ps delay in addition to the programmed value.
The digital delay allows an output to be delayed from 3.5 to 32 VCO cycles. The delay step can be as small as half the period of the clock distribution path. For example, 2-GHz VCO frequency results in 250-ps tuning steps. The digital delay value takes effect on the clock outputs after a SYNC event. Fixed digital delay allows all the outputs to have a known phase relationship upon a SYNC event and is typically performed at start-up.