ZHCSK16A October 2017 – July 2019 LMK04228
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1
Overview
- 9.1.1 Jitter Cleaning
- 9.1.2 JEDEC JESD204B Support
- 9.1.3 Three PLL1 Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*, and CLKin2/CLKin2*)
- 9.1.4 VCXO- and Crystal-Buffered Output
- 9.1.5 Frequency Holdover
- 9.1.6 PLL2 Integrated Loop Filter Poles
- 9.1.7 Internal VCOs
- 9.1.8 Clock Distribution
- 9.1.9 Status Pins
- 9.2 Functional Block Diagrams
- 9.3 Feature Description
- 9.4 Programming
- 9.5
Register Maps
- 9.5.1 Register Map for Device Programming
- 9.5.2
Device Register Descriptions
- 9.5.2.1 System Functions
- 9.5.2.2
(0x100 - 0x138) Device Clock and SYSREF Clock Output Controls
- 9.5.2.2.1 CLKoutX_Y_ODL, CLKoutX_Y_IDL, DCLKoutX_DIV
- 9.5.2.2.2 DCLKoutX_DDLY_CNTH, DCLKoutX_DDLY_CNTL
- 9.5.2.2.3 DCLKoutX_ADLY, DCLKoutX_ADLY_MUX, DCLKout_MUX
- 9.5.2.2.4 DCLKoutX_HS, SDCLKoutY_MUX, SDCLKoutY_DDLY, SDCLKoutY_HS
- 9.5.2.2.5 SDCLKoutY_ADLY_EN, SDCLKoutY_ADLY
- 9.5.2.2.6 DCLKoutX_DDLY_PD, DCLKout_ADLY_PD, DCLKoutX_Y_PD, SDCLKoutY_DIS_MODE, SDCLKoutY_PD
- 9.5.2.2.7 SDCLKoutY_POL, SDCLKoutY_FMT, DCLKoutX_POL, DCLKoutX_FMT
- 9.5.2.3
SYSREF, SYNC, and Device Config
- 9.5.2.3.1 VCO_MUX, OSCout_FMT
- 9.5.2.3.2 SYSREF_CLKin0_MUX, SYSREF_MUX
- 9.5.2.3.3 SYSREF_DIV[12:8], SYSREF_DIV[7:0]
- 9.5.2.3.4 SYSREF_DDLY[12:8], SYSREF_DDLY[7:0]
- 9.5.2.3.5 SYSREF_PULSE_CNT
- 9.5.2.3.6 PLL1_PD, VCO_LDO_PD, VCO_PD, OSCin_PD, SYSREF_GBL_PD, SYSREF_PD, SYSREF_DDLY_PD, SYSREF_PLSR_PD
- 9.5.2.3.7 SYSREF_CLR, SYNC_1SHOT_EN, SYNC_POL, SYNC_EN, SYNC_PLL2_DLD, SYNC_PLL1_DLD, SYNC_MODE
- 9.5.2.3.8 SYNC_DISSYSREF, SYNC_DISX
- 9.5.2.3.9 Fixed Register
- 9.5.2.4 (0x146 - 0x149) CLKin Control
- 9.5.2.5 RESET_MUX, RESET_TYPE
- 9.5.2.6
(0x14B - 0x152) Holdover
- 9.5.2.6.1 LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8]
- 9.5.2.6.2 MAN_DAC[9:8], MAN_DAC[7:0]
- 9.5.2.6.3 DAC_TRIP_LOW
- 9.5.2.6.4 DAC_CLK_MULT, DAC_TRIP_HIGH
- 9.5.2.6.5 DAC_CLK_CNTR
- 9.5.2.6.6 CLKin_OVERRIDE, HOLDOVER_PLL1_DET, HOLDOVER_LOS_DET, HOLDOVER_VTUNE_DET, HOLDOVER_HITLESS_SWITCH, HOLDOVER_EN
- 9.5.2.6.7 HOLDOVER_DLD_CNT[13:8], HOLDOVER_DLD_CNT[7:0]
- 9.5.2.7 (0x153 - 0x15F) PLL1 Configuration
- 9.5.2.8
(0x160 - 0x16E) PLL2 Configuration
- 9.5.2.8.1 PLL2_R[4:0]
- 9.5.2.8.2 PLL2_P, OSCin_FREQ, PLL2_XTAL_EN, PLL2_REF_2X_EN
- 9.5.2.8.3 PLL2_FCAL_DIS
- 9.5.2.8.4 PLL2_N
- 9.5.2.8.5 PLL2_WND_SIZE, PLL2_CP_GAIN, PLL2_CP_POL, PLL2_CP_TRI
- 9.5.2.8.6 SYSREF_REQ_EN, PLL2_DLD_CNT
- 9.5.2.8.7 PLL2_LF_R4, PLL2_LF_R3
- 9.5.2.8.8 PLL2_LF_C4, PLL2_LF_C3
- 9.5.2.8.9 PLL2_LD_MUX, PLL2_LD_TYPE
- 9.5.2.9
(0x16F - 0x1FFF) Misc Registers
- 9.5.2.9.1 Fixed Register
- 9.5.2.9.2 Fixed Register
- 9.5.2.9.3 PLL2_PRE_PD, PLL2_PD
- 9.5.2.9.4 OPT_REG_1
- 9.5.2.9.5 OPT_REG_2
- 9.5.2.9.6 RB_PLL1_LD_LOST, RB_PLL1_LD, CLR_PLL1_LD_LOST
- 9.5.2.9.7 RB_PLL2_LD_LOST, RB_PLL2_LD, CLR_PLL2_LD_LOST
- 9.5.2.9.8 RB_DAC_VALUE(MSB), RB_CLKinX_SEL, RB_CLKinX_LOS
- 9.5.2.9.9 RB_DAC_VALUE
- 9.5.2.9.10 RB_HOLDOVER
- 9.5.2.9.11 SPI_LOCK
- 9.1
Overview
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13器件和文檔支持
- 14機械、封裝和可訂購信息
8.2 Differential Voltage Measurement Terminology
The differential voltage of a differential signal can be described by two different definitions causing confusion when reading data sheets or communicating with other engineers. This section will address the measurement and description of a differential signal so that the reader will be able to understand and distinguish between the two different definitions when used.
The first definition used to describe a differential signal is the absolute value of the voltage potential between the inverting and noninverting signal. The symbol for this first measurement is typically VID or VOD depending on if an input or output voltage is being described.
The second definition used to describe a differential signal is to measure the potential of the noninverting signal with respect to the inverting signal. The symbol for this second measurement is VSS and is a calculated parameter. Nowhere in the IC does this signal exist with respect to ground, it only exists in reference to its differential pair. VSS can be measured directly by oscilloscopes with floating references, otherwise this value can be calculated as twice the value of VOD as described in the first description.
Figure 2 illustrates the two different definitions side-by-side for inputs and Figure 3 illustrates the two different definitions side-by-side for outputs. The VID and VOD definitions show VA and VB DC levels that the noninverting and inverting signals toggle between with respect to ground. VSS input and output definitions show that if the inverting signal is considered the voltage potential reference, the noninverting signal voltage potential is now increasing and decreasing above and below the noninverting reference. Thus the peak-to-peak voltage of the differential signal can be measured.
VID and VOD are often defined as volts (V) and VSS is often defined as volts peak-to-peak (VPP).
Figure 2. Two Different Definitions for
Differential Input Signals
Figure 3. Two Different Definitions for
Differential Output Signals
Refer to application note AN-912 Common Data Transmission Parameters and their Definitions (SNLA036) for more information.