ZHCSK16A October 2017 – July 2019 LMK04228
PRODUCTION DATA.
| PIN | I/O | TYPE | DESCRIPTION | |
|---|---|---|---|---|
| NO. | NAME | |||
| 1 | DCLKout0 | O | Programmable | Device clock output 0. |
| 2 | DCLKout0* | |||
| 3 | SDCLKout1 | O | Programmable | SYSREF / Device clock output 1 |
| 4 | SDCLKout1* | |||
| 5 | RESET/GPO | I | CMOS | Device reset input or GPO |
| 6 | SYNC/SYSREF_REQ | I | CMOS | Synchronization input or SYSREF_REQ for requesting continuous SYSREF. |
| 7, 8, 9 | NC | — | — | Do not connect. These pins must be left floating. |
| 10 | Vcc1_VCO | — | PWR | Power supply for VCO LDO. |
| 11 | LDObyp1 | — | ANLG | LDO Bypass, bypassed to ground with 10-µF capacitor. |
| 12 | LDObyp2 | — | ANLG | LDO Bypass, bypassed to ground with a 0.1-µF capacitor. |
| 13 | SDCLKout3 | O | Programmable | SYSREF / Device Clock output 3. |
| 14 | SDCLKout3* | |||
| 15 | DCLKout2 | O | Programmable | Device clock output 2. |
| 16 | DCLKout2* | |||
| 17 | Vcc2_CG1 | — | PWR | Power supply for clock outputs 2 and 3. |
| 18 | CS* | I | CMOS | Chip Select |
| 19 | SCK | I | CMOS | SPI Clock |
| 20 | SDIO | I/O | CMOS | SPI Data |
| 21 | Vcc3_SYSREF | — | PWR | Power supply for SYSREF divider and SYNC. |
| 22 | SDCLKout5 | O | Programmable | SYSREF / Device clock output 5. |
| 23 | SDCKLout5* | |||
| 24 | DCLKout4 | O | Programmable | Device clock output 4. |
| 25 | DCLKout4* | |||
| 26 | Vcc4_CG2 | — | PWR | Power supply for clock outputs 4, 5, 6 and 7. |
| 27 | DCLKout6 | O | Programmable | Device clock output 6. |
| 28 | DCLKout6* | |||
| 29 | SDCLKout7 | O | Programmable | SYSREF / Device clock output 7. |
| 30 | SDCLKout7* | |||
| 31 | Status_LD1 | I/O | Programmable | Programmable status pin. |
| 32 | CPout1 | O | ANLG | Charge pump 1 output. |
| 33 | Vcc5_DIG | — | PWR | Power supply for the digital circuitry. |
| 34 | CLKin1 | I | ANLG | Reference Clock Input Port 1 for PLL1. |
| 35 | CLKin1* | |||
| 36 | Vcc6_PLL1 | — | PWR | Power supply for PLL1, charge pump 1, holdover DAC |
| 37 | CLKin0 | I | ANLG | Reference Clock Input Port 0 for PLL1. |
| 38 | CLKin0* | |||
| 39 | Vcc7_OSCout | — | PWR | Power supply for OSCout port. |
| 40 | OSCout/CLKin2 | O | Programmable | Buffered output of OSCin port. |
| 41 | OSCout*/CLKin2* | Reference Clock Input Port 2 for PLL1. | ||
| 42 | Vcc8_OSCin | — | PWR | Power supply for OSCin |
| 43 | OSCin | I | ANLG | Feedback to PLL1, Reference input to PLL2. AC-coupled. |
| 44 | OSCin* | |||
| 45 | Vcc9_CP2 | — | PWR | Power supply for PLL2 Charge Pump. |
| 46 | CPout2 | O | ANLG | Charge pump 2 output. |
| 47 | Vcc10_PLL2 | — | PWR | Power supply for PLL2. |
| 48 | Status_LD2 | I/O | Programmable | Programmable status pin. |
| 49 | SDCLKout9 | O | Programmable | SYSREF / Device clock 9 |
| 50 | SDCLKout9* | |||
| 51 | DCLKout8 | O | Programmable | Device clock output 8. |
| 52 | DCLKout8* | |||
| 53 | Vcc11_CG3 | — | PWR | Power supply for clock outputs 8, 9, 10, and 11. |
| 54 | DCLKout10 | O | Programmable | Device clock output 10. |
| 55 | DCLKout10* | |||
| 56 | SDCLKout11 | O | Programmable | SYSREF / Device clock output 11. |
| 57 | SDCLKout11* | |||
| 58 | CLKin_SEL0 | I/O | Programmable | Programmable status pin. |
| 59 | CLKin_SEL1 | I/O | Programmable | Programmable status pin. |
| 60 | SDCLKout13 | O | Programmable | SYSREF / Device clock output 13. |
| 61 | SDCLKout13* | |||
| 62 | DCLKout12 | O | Programmable | Device clock output 12. |
| 63 | DCLKout12* | |||
| 64 | Vcc12_CG0 | — | PWR | Power supply for clock outputs 0, 1, 12, and 13. |
| — | DAP | — | GND | DIE ATTACH PAD, connect to GND. |