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ZHCSNW8A October 2022 – December 2022 LMG2610

PRODUCTION DATA

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RRG|40

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

6.6 Switching Characteristics

1) Symbol definitions: V_DS(ls) = SW to SL voltage; I_DS(ls) = SW to SL current; V_DS(hs) = DH to SW voltage; I_D(hs) = DH to SW current; 2) Unless otherwise noted: voltage, resistance, and capacitance are respect to AGND; -40 °C ≤ T_J ≤ 125 °C; 10 ≤ V_AUX ≤ 26; 7.5 ≤ V_{BST_SW} ≤ 26; V_EN = 5 V; V_INL = 0 V; V_INH = 0 V; R_RDRVL = 0 ?; R_{RDRVH_SW} = 0 ?; R_CS = 100 ?

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
LOW-SIDE GAN POWER FET
t_{d(on)(Idrain)(ls)}	Drain current turn-on delay time	From V_INL > V_INL,IT+ to I_D(ls) > 50 mA, V_BUS = 400 V, L_HB current = 2 A, at below low-side slew rate settings, see GaN Power FET Switching Parameters
		slew rate setting 0 (slowest)	68		ns
		slew rate setting 1	40
		slew rate setting 2	35
		slew rate setting 3 (fastest)	34
t_d(on)(ls)	Turn-on delay time	From V_INL > V_INL,IT+ to V_DS(ls) < 320 V, V_BUS = 400 V, L_HB current = 2 A, at below low-side slew rate settings, see GaN Power FET Switching Parameters
		slew rate setting 0 (slowest)	91		ns
		slew rate setting 1	50
		slew rate setting 2	43
		slew rate setting 3 (fastest)	37
t_r(on)(ls)	Turn-on rise time	From V_DS(ls) < 320 V to V_DS(ls) < 80 V, V_BUS = 400 V, L_HB current = 2 A, at below low-side slew rate settings, see GaN Power FET Switching Parameters
		slew rate setting 0 (slowest)	14.9		ns
		slew rate setting 1	5.6
		slew rate setting 2	3.8
		slew rate setting 3 (fastest)	1.9
t_d(off)(ls)	Turn-off delay time	From V_INL < V_INL,IT– to V_DS(ls) > 80 V, V_BUS = 400 V, L_HB current = 2 A, (independent of slew rate setting), see GaN Power FET Switching Parameters	43		ns
t_f(off)(ls)	Turn-off fall time	From V_DS(ls) > 80 V to V_DS(ls) > 320 V, V_BUS = 400 V, L_HB current = 2 A, (independent of slew rate setting), see GaN Power FET Switching Parameters	12.5		ns
	Turn-on slew rate	From V_DS(ls) < 250 V to V_DS(ls) < 150 V, T_J = 25 ℃, V_BUS = 400 V, L_HB current = 2 A, at below low-side slew rate settings, see GaN Power FET Switching Parameters
		slew rate setting 0 (slowest)	20		V/ns
		slew rate setting 1	50
		slew rate setting 2	70
		slew rate setting 3 (fastest)	140
HIGH-SIDE GAN POWER FET
t_{d(on)(Idrain)(hs)}	Drain current turn-on delay time	From V_INH > V_INH,IT+ to I_D(hs) > 50 mA, V_BUS = 400 V, L_HB current = 2 A, at below high-side slew rate settings, see GaN Power FET Switching Parameters
		slew rate setting 0 (slowest)	60		ns
		slew rate setting 1	34
		slew rate setting 2	31
		slew rate setting 3 (fastest)	28
t_d(on)(hs)	Turn-on delay time	From V_INH > V_INH,IT+ to V_DS(hs) < 320 V, V_BUS = 400 V, L_HB current = 2 A, at below high-side slew rate settings, see GaN Power FET Switching Parameters
		slew rate setting 0 (slowest)	86		ns
		slew rate setting 1	46
		slew rate setting 2	39
		slew rate setting 3 (fastest)	32
t_r(on)(hs)	Turn-on rise time	From V_DS(hs) < 320 V to V_DS(hs) < 80 V, V_BUS = 400 V, L_HB current = 2 A, at below high-side slew rate settings, see GaN Power FET Switching Parameters
		slew rate setting 0 (slowest)	13.1		ns
		slew rate setting 1	4.7
		slew rate setting 2	3.2
		slew rate setting 3 (fastest)	1.7
t_d(off)(hs)	Turn-off delay time	From V_INH < V_INH,IT–to V_DS(hs) > 80 V, V_BUS = 400 V, L_HB current = 2 A, (independent of slew rate setting), see GaN Power FET Switching Parameters	37		ns
t_f(off)(hs)	Turn-off fall time	From V_DS(hs) > 80 V to V_DS(hs) > 320 V, V_BUS = 400 V, L_HB current = 2 A, (independent of slew rate setting), see GaN Power FET Switching Parameters	12.5		ns
	Turn-on slew rate	From V_DS(hs) < 250 V to V_DS(hs) < 150 V, T_J = 25 ℃, V_BUS = 400 V, L_HB current = 2 A, at below high-side slew rate settings, see GaN Power FET Switching Parameters
		slew rate setting 0 (slowest)	20		V/ns
		slew rate setting 1	65
		slew rate setting 2	90
		slew rate setting 3 (fastest)	165
CS
	Settling time	From I_CS > 0.1I_{CS(src)(final)} to I_CS < 0.9I_{CS(src)(final)}, Low-side enabled into a 2 A load, 0 V ≤ V_CS ≤ 2 V,		35	ns
EN
	EN wake-up time	V_INL = 5 V, From V_EN > V_IT+ to I_D(ls) > 10 mA	1		μs
BST
	Start-up time from deep BST to SW discharge	From V_{BST_SW} ≥ V_{BST_SW,T+(UVLO)} to high-side reacts to INH rising edge with V_{BST_SW} rising from 0 V to 10 V in 1 μs	5		μs
	Start-up time from shallow BST to SW discharge	From V_{BST_SW} ≥ V_{BST_SW,T+(UVLO)} to high-side reacts to INH rising edge with V_{BST_SW} rising from 5 V to 10 V in 0.5 μs	2		μs