The BST UVLO voltage is with respect to the SW pin. The BST UVLO only controls the high-side GaN power FET. The BST UVLO does not control the low-side GaN power FET. The BST UVLO consists of two separate UVLO functions to create a two-level BST UVLO. The upper BST UVLO is called the BST Turn-On UVLO and only controls if the high-side GaN power FET is turned on. The lower BST UVLO is called the BST Turn-Off UVLO and only controls if the high-side GaN power FET is turned off after the high-side GaN power FET is turned on. The operation of the two-level UVLO is not the same as a single UVLO with wide hysteresis.

Figure 8-4 shows the BST UVLO operation. The BST Turn-On UVLO prevents the high-side GaN power FET from turning on at a INH logic-high rising edge if the BST-to-SW voltage is below the BST Turn-On UVLO voltage - INH pulses #1, #2, and #5. After the high-side GaN power FET is successfully turned-on, the BST Turn-On UVLO is ignored and the BST Turn-Off UVLO output is watched for the remainder of the INH logic-high pulse - INH pulses #3, #4, and #6. The BST Turn-Off UVLO turns off the high-side GaN power FET for the remainder of the INH logic-high pulse if the BST-to-SW voltage falls below the BST Turn-Off UVLO voltage - INH pulse #6.

The effective voltage hysteresis of the two-level BST UVLO is the difference between the upper and lower BST UVLO voltages. A single-level BST UVLO can be implemented with the same hysteresis but allows subsequent high-side GaN power FET turn on anywhere in the hysteresis range. The two-level UVLO design prevents any turn on in the hysteresis range. A single-level BST UVLO would allow INH pulse #5 to turn on the high-side GaN power FET.

The two-level BST UVLO allows a wide hysteresis while making sure the BST-to-SW capacitor is adequately charged at the beginning of every INH pulse. The wide hysteresis allows a smaller BST-to-SW capacitor to be used which is useful for faster high-side start-up time. The adequate capacitor charge at the beginning of the INH pulse helps make sure the high-side GaN power FET is not turned-off early in the INH pulse which can create undesired spike voltages in the converter.