ZHCSNW8A October 2022 – December 2022 LMG2610
PRODUCTION DATA
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| Supply voltage | AUX | 10 | 26 | V | ||
| Supply voltage to SW | BST | 7.5 | 26 | V | ||
| Input voltage | EN, INL, INH | 0 | VAUX | V | ||
| Pull-up voltage on open-drain output | FLT | 0 | VAUX | V | ||
| VIH | High-level input voltage | EN, INL, INH | 2.5 | V | ||
| VIL | Low-level input voltage | 0.6 | V | |||
| ID(peak)(ls) | Low-side drain (SW to SL) peak current, FET on | –3.2 | 5.4 | A | ||
| ID(peak)(hs) | High-side drain (DH to SW) peak current, FET on | –2 | 3 | A | ||
| CAUX | AUX to AGND capacitance from external bypass capacitor | 3 x CBST | μF | |||
| CBST_SW | BST to SW capacitance from external bypass capacitor | 0.010 | μF | |||
| RRDRVL | RDRVL to AGND resistance from external slew-rate control resistor to configure below low-side slew rate settings | |||||
| slew rate setting 0 (slowest) | 90 | 120 | open | kΩ | ||
| slew rate setting 1 | 42.5 | 47 | 51.5 | kΩ | ||
| slew rate setting 2 | 20 | 22 | 24 | kΩ | ||
| slew rate setting 3 (fastest) | 0 | 5.6 | 11 | kΩ | ||
| RRDRVH_SW | RDRVH to SW resistance from external slew-rate control resistor to configure below high-side slew rate settings | |||||
| slew rate setting 0 (slowest) | 90 | 120 | open | kΩ | ||
| slew rate setting 1 | 42.5 | 47 | 51.5 | kΩ | ||
| slew rate setting 2 | 20 | 22 | 24 | kΩ | ||
| slew rate setting 3 (fastest) | 0 | 5.6 | 11 | kΩ | ||