The EN pin is used to toggle the device between the active and standby modes described in Device Functional Modes.

The INL pin is used to turn the low-side GaN power FET on and off.

The INH pin is used to turn the high-side GaN power FET on and off.

The input control pins have a typical 1-V input-voltage-threshold hysteresis for noise immunity. The pins also have a typical 400 k? pull-down resistance to protect against floating inputs. The 400 k? saturates for typical input voltages above 4 V to limit the maximum input pull-down current to a typical 10 uA.

The INL turn-on action is impacted by the following conditions 1) Standby Mode, 2) AUX UVLO, 3) INH in control of Interlock, 4) Low-Side Over-Current Protection, and 5) Over-Temperature Protection.

The INH turn-on action is impacted by the following conditions 1) Standby Mode, 2) AUX UVLO, 3) INL in control of Interlock, 4) High-Side Over-Current Protection, and 5) Over-Temperature Protection.

The Standby Mode, AUX UVLO, and Over-Temperature Protection are the universal INL / INH blocking conditions. These conditions hold both GaN half-bridge power FETs off independent of INL and INH. Figure 8-3 shows the Universal Blocking Condition Operation. Note that the high-side FET does not turn on at transistion #4. INH only turns on the high-side FET if there is no universal blocking condition when INH goes to logic high. This avoids an incomplete high-side FET turn-on period which can create undesired spike voltages in the converter.