ZHCSB29I September   2009  – October  2019 DS90UR905Q-Q1 , DS90UR906Q-Q1

PRODUCTION DATA.  

1. 1 特性
2. 2 應(yīng)用
3. 3 說(shuō)明
   1.     Device Images
      1.      703A I2C
4. 4 修訂歷史記錄
5. 5 說(shuō)明 （續(xù)）
6. 6 Pin Configuration and Functions
   1.     DS90UR905Q-Q1 Serializer Pin Functions
   2.     DS90UR906Q-Q1 Deserializer Pin Functions
7. 7 Specifications
   1. 7.1  Absolute Maximum Ratings
   2. 7.2  ESD Ratings
   3. 7.3  Recommended Operating Conditions
   4. 7.4  Thermal Information
   5. 7.5  Serializer DC Electrical Characteristics
   6. 7.6  Deserializer DC Electrical Characteristics
   7. 7.7  DC and AC Serial Control Bus Characteristics
   8. 7.8  Timing Requirements for DC and AC Serial Control Bus
   9. 7.9  Timing Requirements for Serializer PCLK
   10. 7.10 Timing Requirements for Serial Control Bus
   11. 7.11 Switching Characteristics: Serializer
   12. 7.12 Switching Characteristics: Deserializer
   13. 7.13 Typical Characteristics
8. 8 Detailed Description
   1. 8.1 Overview
   2. 8.2 Functional Block Diagrams
   3. 8.3 Feature Description
      1. 8.3.1 Data Transfer
      2. 8.3.2 Video Control Signal Filter — Serializer and Deserializer
      3. 8.3.3 Serializer Functional Description
         1. 8.3.3.1 EMI Reduction Features
            1. 8.3.3.1.1 Serializer Spread Spectrum Compatibility
         2. 8.3.3.2 Signal Quality Enhancers
            1. 8.3.3.2.1 Serializer VOD Select (VODSEL)
            2. 8.3.3.2.2 Serializer De-Emphasis (De-Emph)
         3. 8.3.3.3 Power-Saving Features
            1. 8.3.3.3.1 Serializer Power-down Feature (PDB)
            2. 8.3.3.3.2 Serializer Stop Clock Feature
            3. 8.3.3.3.3 1.8-V or 3.3-V VDDIO Operation
         4. 8.3.3.4 Serializer Pixel Clock Edge Select (RFB)
         5. 8.3.3.5 Optional Serial Bus Control
         6. 8.3.3.6 Optional BIST Mode
      4. 8.3.4 Deserializer Functional Description
         1. 8.3.4.1  Signal Quality Enhancers
            1. 8.3.4.1.1 Deserializer Input Equalizer Gain (EQ)
         2. 8.3.4.2  EMI Reduction Features
            1. 8.3.4.2.1 Deserializer Output Slew (OS_PCLK/DATA)
            2. 8.3.4.2.2 Deserializer Common-Mode Filter Pin (CMF) — Optional
            3. 8.3.4.2.3 Deserializer SSCG Generation — Optional
            4. 8.3.4.2.4 1.8-V or 3.3-V VDDIO Operation
         3. 8.3.4.3  Power-Saving Features
            1. 8.3.4.3.1 Deserializer Power-Down Feature (PDB)
            2. 8.3.4.3.2 Deserializer Stop Stream SLEEP Feature
         4. 8.3.4.4  Deserializer CLOCK-DATA RECOVERY STATUS FLAG (LOCK) and OUTPUT STATE SELECT (OSS_SEL)
         5. 8.3.4.5  Deserializer Oscillator Output (Optional)
         6. 8.3.4.6  Deserializer OP_LOW (Optional)
         7. 8.3.4.7  Deserializer Pixel Clock Edge Select (RFB)
         8. 8.3.4.8  Deserializer Control Signal Filter (Optional)
         9. 8.3.4.9  Deserializer Low Frequency Optimization (LF_Mode)
         10. 8.3.4.10 Deserializer Map Select
         11. 8.3.4.11 Deserializer Strap Input Pins
         12. 8.3.4.12 Optional Serial Bus Control
         13. 8.3.4.13 Optional BIST Mode
      5. 8.3.5 Built-In Self Test (BIST)
         1. 8.3.5.1 Sample BIST Sequence
         2. 8.3.5.2 BER Calculations
      6. 8.3.6 Optional Serial Bus Control
   4. 8.4 Device Functional Modes
      1. 8.4.1 Serializer and Deserializer Operating Modes and Backward Compatibility (CONFIG[1:0])
   5. 8.5 Register Maps
9. 9 Application and Implementation
   1. 9.1 Application Information
      1. 9.1.1 Display Application
      2. 9.1.2 Live Link Insertion
      3. 9.1.3 Alternate Color / Data Mapping
   2. 9.2 Typical Applications
      1. 9.2.1 DS90UR905Q-Q1 Typical Connection
         1. 9.2.1.1 Design Requirements
         2. 9.2.1.2 Detailed Design Procedure
         3. 9.2.1.3 Application Curves
      2. 9.2.2 DS90UR906Q-Q1 Typical Connection
         1. 9.2.2.1 Design Requirements
         2. 9.2.2.2 Detailed Design Procedure
         3. 9.2.2.3 Application Curves
10. 10Power Supply Recommendations
    1. 10.1 Power Up Requirements and PDB Pin
11. 11Layout
    1. 11.1 Layout Guidelines
       1. 11.1.1 Transmission Media
       2. 11.1.2 LVDS Interconnect Guidelines
    2. 11.2 Layout Example
12. 12器件和文檔支持
    1. 12.1 文檔支持
       1. 12.1.1 相關(guān)文檔
    2. 12.2 相關(guān)鏈接
    3. 12.3 社區(qū)資源
    4. 12.4 商標(biāo)
    5. 12.5 靜電放電警告
    6. 12.6 Glossary
13. 13機(jī)械、封裝和可訂購(gòu)信息