ZHCSB29I September 2009 – October 2019 DS90UR905Q-Q1 , DS90UR906Q-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 說明 （續）
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Serializer DC Electrical Characteristics
- 7.6 Deserializer DC Electrical Characteristics
- 7.7 DC and AC Serial Control Bus Characteristics
- 7.8 Timing Requirements for DC and AC Serial Control Bus
- 7.9 Timing Requirements for Serializer PCLK
- 7.10 Timing Requirements for Serial Control Bus
- 7.11 Switching Characteristics: Serializer
- 7.12 Switching Characteristics: Deserializer
- 7.13 Typical Characteristics
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagrams
- 8.3
Feature Description
- 8.3.1 Data Transfer
- 8.3.2 Video Control Signal Filter — Serializer and Deserializer
- 8.3.3 Serializer Functional Description
- 8.3.4
Deserializer Functional Description
- 8.3.4.1 Signal Quality Enhancers
- 8.3.4.2 EMI Reduction Features
- 8.3.4.3 Power-Saving Features
- 8.3.4.4 Deserializer CLOCK-DATA RECOVERY STATUS FLAG (LOCK) and OUTPUT STATE SELECT (OSS_SEL)
- 8.3.4.5 Deserializer Oscillator Output (Optional)
- 8.3.4.6 Deserializer OP_LOW (Optional)
- 8.3.4.7 Deserializer Pixel Clock Edge Select (RFB)
- 8.3.4.8 Deserializer Control Signal Filter (Optional)
- 8.3.4.9 Deserializer Low Frequency Optimization (LF_Mode)
- 8.3.4.10 Deserializer Map Select
- 8.3.4.11 Deserializer Strap Input Pins
- 8.3.4.12 Optional Serial Bus Control
- 8.3.4.13 Optional BIST Mode
- 8.3.5 Built-In Self Test (BIST)
- 8.3.6 Optional Serial Bus Control
- 8.4 Device Functional Modes
- 8.5 Register Maps
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
8.3.4.6 Deserializer OP_LOW (Optional)
The OP_ LOW feature is used to hold the LVCMOS outputs (except the LOCK output) at a LOW state. The user must toggle the OP_LOW Set / Reset register bit to release the outputs to the normal toggling state.
NOTE
The release of the outputs can only occur when LOCK is HIGH. When the OP_LOW feature is enabled, anytime LOCK = LOW, the LVCMOS outputs will toggle to a LOW state again. The OP_ LOW strap pin feature is assigned to output PASS pin 42.
Restrictions on other straps:
- Other straps should not be used in order to keep RGB[7:0], HS, VS, DE, and PCLK at a true LOW state. Other features should be selected through I2C.
- OSS_SEL function is not available when O/P_LOW is tied H.
Outputs RGB[7:0], HSYNC, VSYNC, DE, and PCLK are in TRI-STATE before PDB toggles HIGH because the OP_LOW strap value has not been recognized until the DS90UR906Q-Q1 powers up. Figure 30 shows the user controlled release of OP_LOW and automatic reset of OP_LOW set on the falling edge of LOCK. Figure 31 shows the user controlled release of OP_LOW and manual reset of OP_LOW set.
NOTE
Manual reset of OP_LOW can only occur when LOCK is H.
Figure 30. OP_LOW Auto Set 
Figure 31. OP_LOW Manual Set/Reset