ZHCSB29I September 2009 – October 2019 DS90UR905Q-Q1 , DS90UR906Q-Q1
PRODUCTION DATA.
The DS90UR90xQ-Q1 chipset transmits and receives 27-bits of data (24-high speed color bits and 3 low speed video control signals) over a single serial FPD-Link II pair operating at 140Mbps to 1.82Gbps. The serial stream also contains an embedded clock, video control signals and the DC-balance information which enhances signal quality and supports AC coupling. The pair is intended for use with each other but is backward-compatible with previous generations of FPD-Link II as well.
The deserializer can attain lock to a data stream without the use of a separate reference clock source, which greatly simplifies system complexity and overall cost. The deserializer also synchronizes to the serializer regardless of the data pattern, delivering true automatic plug and lock performance. It can lock to the incoming serial stream without the need of special training patterns or sync characters. The deserializer recovers the clock and data by extracting the embedded clock information, validating and then deserializing the incoming data stream providing a parallel LVCMOS video bus to the display.
The DS90UR90xQ-Q1 chipset can operate in 24-bit color depth (with VS,HS,DE encoded in the DCA bit) or in 18-bit color depth (with VS, HS, DE encoded in DCA or mapped into the high-speed data bits). In 18–bit color applications, the three video signals maybe sent encoded via the DCA bit (restrictions apply) or sent as data bits along with three additional general-purpose signals.
Functional Block Diagrams shows the diagrams for the chipsets.