ZHCSB29I September 2009 – October 2019 DS90UR905Q-Q1 , DS90UR906Q-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 說明 （續）
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Serializer DC Electrical Characteristics
- 7.6 Deserializer DC Electrical Characteristics
- 7.7 DC and AC Serial Control Bus Characteristics
- 7.8 Timing Requirements for DC and AC Serial Control Bus
- 7.9 Timing Requirements for Serializer PCLK
- 7.10 Timing Requirements for Serial Control Bus
- 7.11 Switching Characteristics: Serializer
- 7.12 Switching Characteristics: Deserializer
- 7.13 Typical Characteristics
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagrams
- 8.3
Feature Description
- 8.3.1 Data Transfer
- 8.3.2 Video Control Signal Filter — Serializer and Deserializer
- 8.3.3 Serializer Functional Description
- 8.3.4
Deserializer Functional Description
- 8.3.4.1 Signal Quality Enhancers
- 8.3.4.2 EMI Reduction Features
- 8.3.4.3 Power-Saving Features
- 8.3.4.4 Deserializer CLOCK-DATA RECOVERY STATUS FLAG (LOCK) and OUTPUT STATE SELECT (OSS_SEL)
- 8.3.4.5 Deserializer Oscillator Output (Optional)
- 8.3.4.6 Deserializer OP_LOW (Optional)
- 8.3.4.7 Deserializer Pixel Clock Edge Select (RFB)
- 8.3.4.8 Deserializer Control Signal Filter (Optional)
- 8.3.4.9 Deserializer Low Frequency Optimization (LF_Mode)
- 8.3.4.10 Deserializer Map Select
- 8.3.4.11 Deserializer Strap Input Pins
- 8.3.4.12 Optional Serial Bus Control
- 8.3.4.13 Optional BIST Mode
- 8.3.5 Built-In Self Test (BIST)
- 8.3.6 Optional Serial Bus Control
- 8.4 Device Functional Modes
- 8.5 Register Maps
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
6 Pin Configuration and Functions
RHS Package
48-Pin WQFN
Top View
DS90UR905Q-Q1 Serializer Pin Functions(1)
| PIN | I/O, TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| LVCMOS PARALLEL INTERFACE | |||
| B[7:0] | 2, 1, 48, 47, 46, 45, 44, 43 | I, LVCMOS
with pulldown |
BLUE parallel interface data input pins
(MSB = 7, LSB = 0) |
| DE | 5 | I, LVCMOS
with pulldown |
Data enable input
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the control signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition pulse when the control signal filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2 transitions per 130 PCLKs. |
| G[7:0] | 42, 41, 40, 39, 38, 37, 36, 35 | I, LVCMOS
with pulldown |
GREEN parallel interface data input pins
(MSB = 7, LSB = 0) |
| HS | 3 | I, LVCMOS
with pulldown |
Horizontal Sync Input
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the control signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition pulse when the control signal filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2 transitions per 130 PCLKs. |
| PCLK | 10 | I, LVCMOS
with pulldown |
Pixel clock input
Latch edge set by RFB function. |
| R[7:0] | 34, 33, 32, 29, 28, 27, 26, 25 | I, LVCMOS
with pulldown |
RED parallel interface data input pins
(MSB = 7, LSB = 0) |
| VS | 4 | I, LVCMOS
with pulldown |
Vertical sync input
Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width is 130 PCLKs. |
| CONTROL AND CONFIGURATION | |||
| BISTEN | 31 | I, LVCMOS
with pulldown |
BIST mode — optional
BISTEN = 1, BIST is enabled BISTEN = 0, BIST is disabled |
| CONFIG[1:0] | 13, 12 | I, LVCMOS
with pulldown |
Operating modes — pin or register control
Determine the operating mode of the DS90UR905 and interfacing device. CONFIG[1:0] = 00: interfacing to DS90UR906Q-Q1, control signal filter DISABLED CONFIG[1:0] = 01: interfacing to DS90UR906Q-Q1, control signal filter ENABLED CONFIG[1:0] = 10: interfacing to DS90UR124, DS99R124 CONFIG[1:0] = 11: interfacing to DS90C124 |
| De-Emph | 23 | I, Analog
with pullup |
De-emphasis control — pin or register control
De-emph = open (float) - disabled To enable de-emphasis, tie a resistor from this pin to GND or control via register (see Table 2). |
| ID[x] | 6 | I, Analog | Serial control bus device ID address select — optional
Resistor-to-ground and 10-kΩ pullup to 1.8-V rail (see Table 11). |
| PDB | 21 | I, LVCMOS
with pulldown |
Power-down mode input
PDB = 1, serializer is enabled (normal operation). Refer to Power Up Requirements and PDB Pin. PDB = 0, serializer is powered down When the serializer is in the power-down state, the driver outputs (DOUT±) are both logic high, the PLL is shutdown, IDD is minimized. Control registers are RESET. |
| RES[2:0] | 18, 16, 15 | I, LVCMOS
with pulldown |
Reserved - tie LOW |
| RFB | 11 | I, LVCMOS
with pulldown |
Pixel clock input latch edge select — pin or register control
RFB = 1, parallel interface data and control signals are latched on the rising clock edge. RFB = 0, parallel interface data and control signals are latched on the falling clock edge. |
| SCL | 8 | I, LVCMOS | Serial control bus clock input - optional
SCL requires an external pullup resistor to VDDIO. |
| SDA | 9 | I/O, LVCMOS
Open-Drain |
Serial control bus data input/output - optional
SDA requires an external pullup resistor VDDIO. |
| VODSEL | 24 | I, LVCMOS
with pulldown |
Differential driver output voltage select — pin or register control
VODSEL = 1, LVDS VOD is ±420 mV, 840 mVp-p (typical) — long cable / de-emp applications VODSEL = 0, LVDS VOD is 280 mV, 560 mVp-p (typical) |
| FPD-LINK II SERIAL INTERFACE | |||
| DOUT+ | 20 | O, LVDS | True output
The output must be AC-coupled with a 100-nF capacitor. |
| DOUT- | 19 | O, LVDS | Inverting output
The output must be AC-coupled with a 100-nF capacitor. |
| POWER AND GROUND(2) | |||
| GND | DAP | Ground | DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connect to the ground plane (GND) with at least 9 vias. |
| VDDHS | 17 | Power | TX high-speed logic power, 1.8 V ±5% |
| VDDL | 7 | Power | Logic power, 1.8 V ±5% |
| VDDP | 14 | Power | PLL power, 1.8 V ±5% |
| VDDIO | 30 | Power | LVCMOS I/O power, 1.8 V ±5% or 3.3 V ±10% |
| VDDTX | 22 | Power | Output Driver power, 1.8 V ±5% |
(1) 1 = HIGH, 0 = LOW
(2) The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms, then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
DS90UR906Q-Q1 Deserializer Pin Functions(1)
| PIN | I/O, TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| LVCMOS PARALLEL INTERFACE | |||
| B[7:0] | 9, 10, 11, 12, 14, 17, 18, 19 | I, STRAP,
O, LVCMOS |
BLUE parallel interface data output pins (MSB = 7, LSB = 0)
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (see Table 6). These pins are inputs during power up (see Deserializer Strap Input Pins). |
| DE | 6 | O, LVCMOS | Data enable output
In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 6). Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the control signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition pulse when the control signal filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2 transitions per 130 PCLKs. |
| G[7:0] | 20, 21, 22, 23, 25, 26, 27, 28 | I, STRAP,
O, LVCMOS |
GREEN parallel interface data output pins (MSB = 7, LSB = 0)
In power down (PDB = 0), outputs are controlled by the OSS_SEL (see Table 6). These pins are inputs during power up (see Deserializer Strap Input Pins). |
| HS | 8 | O, LVCMOS | Horizontal sync output
In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 6). Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the control signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition pulse when the control signal filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2 transitions per 130 PCLKs. |
| LOCK | 32 | O, LVCMOS | LOCK status output
LOCK = 1, PLL is Locked, outputs are active LOCK = 0, PLL is unlocked, RGB[7:0], HS, VS, DE and PCLK output states are controlled by OSS_SEL (see Table 6). May be used as link status or to flag when video data is active (ON/OFF). |
| PASS | 42 | O, LVCMOS | PASS output (BIST mode)
PASS = 1, error free transmission PASS = 0, one or more errors were detected in the received payload Route to test point for monitoring, or leave open if unused. |
| PCLK | 5 | O, LVCMOS | Pixel clock output
In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 6). Strobe edge set by RFB function. |
| R[7:0] | 33, 34, 35, 36, 37, 39, 40, 41 | I, STRAP,
O, LVCMOS |
RED parallel interface data output pins (MSB = 7, LSB = 0)
In power down (PDB = 0), outputs are controlled by the OSS_SEL (see Table 6). These pins are inputs during power up (see Deserializer Strap Input Pins). |
| VS | 7 | O, LVCMOS | Vertical sync output
In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 6). Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width is 130 PCLKs. |
| CONTROL AND CONFIGURATION — STRAP PINS
For a HIGH state, use a 10-kΩ pullup to VDDIO; for a LOW state, the IO includes an internal pulldown. The STRAP pins are read upon power up and set device configuration. Pin Number listed along with shared RGB output name in square brackets. |
|||
| CONFIG[1:0] | 10 [B6],
9 [B7] |
STRAP
I, LVCMOS with pulldown |
Operating modes — pin or register control
These pins determine the operating mode of the DS90UR906 and interfacing device. CONFIG[1:0] = 00: interfacing to DS90UR905Q-Q1, control signal filter DISABLED CONFIG[1:0] = 01: interfacing to DS90UR905Q-Q1, control signal filter ENABLED CONFIG[1:0] = 10: interfacing to DS90UR241 CONFIG[1:0] = 11: interfacing to DS90C241 |
| EQ[3:0] | 20 [G7],
21 [G6], 22 [G5], 23 [G4] |
STRAP
I, LVCMOS with pulldown |
Receiver input equalization — pin or register control (see Table 3). |
| LF_MODE | 12 [B4] | STRAP
I, LVCMOS with pulldown |
SSCG low-frequency mode — pin or register control
Only required when SSCG is enabled, otherwise LF_MODE condition is a DON’T CARE (X). LF_MODE = 1, SSCG in low-frequency mode (PCLK = 5 to 20 MHz) LF_MODE = 0, SSCG in high-frequency mode (PCLK = 20 to 65 MHz) |
| MAP_SEL[1:0] | 40 [R1],
41 [R0] |
STRAP
I, LVCMOS with pulldown |
Bit mapping backward compatibility / DS90UR241 options — pin or register control
Normal setting to b'00 (see Table 9). |
| OP_LOW | 42 PASS | STRAP
I, LVCMOS with pulldown |
Outputs held LOW when LOCK = 1 — pin or register control
See (2) OP_LOW = 1: all outputs are held LOW during power up until released by programming OP_LOW release / set register HIGH See (3) See Figure 30 and Figure 31. OP_LOW = 0: all outputs toggle normally as soon as LOCK goes HIGH (default). |
| OS_DATA | 14 [B3] | STRAP
I, LVCMOS with pulldown |
Data output slew select — pin or register control
OS_DATA = 1, increased DATA slew OS_DATA = 0, normal (default) |
| OSC_SEL[2:0] | 26 [G2],
27 [G1], 28 [G0] |
STRAP
I, LVCMOS with pulldown |
Oscillator select — pin or register control (see Table 7 and Table 8). |
| OS_PCLK | 11 [B5] | STRAP
I, LVCMOS with pulldown |
PCLK output slew select — pin or register control
OS_PCLK = 1, increased PCLK slew OS_PCLK = 0, normal (default) |
| OSS_SEL | 17 [B2] | STRAP
I, LVCMOS with pulldown |
Output sleep state select — pin or register control
See (4) OSS_SEL is used in conjunction with PDB to determine the state of the outputs in power down (Sleep) (see Table 6). |
| RFB | 18 [B1] | STRAP
I, LVCMOS with pulldown |
Pixel clock output strobe edge select — pin or register control
RFB = 1, parallel interface data and control signals are strobed on the rising clock edge. RFB = 0, parallel interface data and control signals are strobed on the falling clock edge. |
| SSC[3:0] | 34 [R6],
35 [R5], 36 [R4], 37 R[3] |
STRAP
I, LVCMOS with pulldown |
Spread spectrum clock generation (SSCG) range select — pin or register control
See Table 4 and Table 5. |
| CONTROL AND CONFIGURATION | |||
| BISTEN | 44 | I, LVCMOS
with pulldown |
BIST enable input — optional
BISTEN = 1, BIST is enabled BISTEN = 0, BIST is disabled |
| ID[x] | 56 | I, Analog | Serial control bus device ID address select — optional
Resistor-to-ground and 10-kΩ pullup to 1.8-V rail (see Table 10). |
| NC | 1, 15, 16, 30, 31, 45, 46, 60 | — | Not connected
Leave pin open (float) |
| PDB | 59 | I, LVCMOS
with pulldown |
Power-down mode input
PDB = 1, deserializer is enabled (normal operation). Refer to Power Up Requirements and PDB Pin. PDB = 0, deserializer is in power down. When the deserializer is in the power-down state, the LVCMOS output state is determined by Table 6. Control Registers are RESET. |
| RES | 47 | I, LVCMOS
with pulldown |
Reserved - tie LOW |
| SCL | 3 | I, LVCMOS | Serial control bus clock input — optional
SCL requires an external pullup resistor to VDDIO. |
| SDA | 2 | I/O, LVCMOS
Open-Drain |
Serial control bus data input/output — optional
SDA requires an external pullup resistor to VDDIO. |
| FPD-LINK II SERIAL INTERFACE | |||
| CMF | 51 | I, Analog | Common-mode filter
VCM center-tap is a virtual ground which may be AC coupled to ground to increase receiver common-mode noise immunity. Recommended value is 0.1 μF or higher. |
| CMLOUTN | 53 | O, LVDS | Test monitor pin — EQ waveform
NC or connect to test point. Requires serial bus control to enable. |
| CMLOUTP | 52 | O, LVDS | Test monitor pin — EQ waveform
NC or connect to test point. Requires serial bus control to enable. |
| RIN+ | 49 | I, LVDS | True input. The input must be AC coupled with a 100-nF capacitor. |
| RIN- | 50 | I, LVDS | Inverting input. The input must be AC coupled with a 100-nF capacitor. |
| POWER AND GROUND(2) | |||
| GND | DAP | Ground | DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connected to the ground plane (GND) with at least 9 vias. |
| VDDCMLO | 54 | Power | RX high-speed logic power, 1.8 V ±5% |
| VDDL | 29 | Power | Logic power, 1.8 V ±5% |
| VDDIO | 13, 24, 38 | Power | LVCMOS I/O power, 1.8 V ±5% or 3.3 V ±10% (VDDIO) |
| VDDIR | 48 | Power | Input power, 1.8 V ±5% |
| VDDPR | 57 | Power | PLL power, 1.8 V ±5% |
| VDDR | 43, 55 | Power | RX high-speed logic power, 1.8 V ±5% |
| VDDSC | 4, 58 | Power | SSCG power, 1.8 V ±5% |
(1) 1 = HIGH, 0 = LOW
(2) It is not recommended to use any other strap options with this strap function
(3) Before the device is powered up, the outputs are in tri-state.
(4) OSS_SEL strap cannot be used if OP_LOW =1