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ZHCSG37C September 2016 – December 2022 DS90UB934-Q1

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

RGZ|48
- MPQF123F

散熱焊盤機械數據 (封裝 | 引腳)

RGZ|48
- QFND014T

訂購信息

4.5 DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER		TEST CONDITIONS		PIN OR FREQUENCY	MIN	TYP	MAX	UNIT
TOTAL POWER CONSUMPTION
P_T	Total Power Consumption normal operation See Figure 4-5	Worst Case pattern Default registers		V_(VDD18) = V_(VDDIO) = 1.89 V		500	685	mW
P_T	Total Power Consumption normal operation See Figure 4-5	Worst Case pattern Default registers		V_(VDD18) = 1.89 V, V_(VDDIO) = 3.6 V		900	1125	mW
SUPPLY CURRENT
I_DD	Deserializer Supply Current (includes load current). See Figure 4-5.	f = 100 MHz, 10-bit mode V_(VDD18) = 1.89 V Worst Case Pattern, Default Registers C_L = 8 pF	V_(VDDIO) = 1.89 V OR 3.6 V	VDD18			250	mA
			V_(VDDIO) = 1.89 V	VDDIO			60
			V_(VDDIO) = 3.6 V	VDDIO			145
		f = 100 MHz, 12-bit HF mode V_(VDD18) = 1.89 V Worst Case Pattern, Default Registers C_L = 8 pF	V_(VDDIO) = 1.89 V OR 3.6 V	VDD18			270
			V_(VDDIO) = 1.89 V	VDDIO			90
			V_(VDDIO) = 3.6 V	VDDIO			170
		f = 50 MHz, 12-bit LF mode V_(VDD18) = 1.89 V Worst Case Pattern, Default Registers C_L = 8 pF	V_(VDDIO) = 1.89 V OR 3.6 V	VDD18			240
			V_(VDDIO) = 1.89 V	VDDIO			80
			V_(VDDIO) = 3.6 V	VDDIO			155
I_DDZ	Deserializer Power Down Supply Current	V_(VDD18) = 1.89 V, V_(VDDIO) = 3.6V PDB = L, All other LVCMOS inputs = 0V, Default Registers		VDD18			30	mA
I_DDZ	Deserializer Power Down Supply Current			VDDIO			10	mA
1.8-V LVCMOS I/O⁽¹⁾
V_OH	High Level Output Voltage	I_OH = –2 mA	V_(VDDIO) = 1.71 V to 1.89 V	ROUT[11:0], HSYNC, VSYNC, LOCK, PASS	V_(VDDIO) – 0.45		V_(VDDIO)	V
V_OL	Low Level Output Voltage	I_OL = 2 mA	V_(VDDIO) = 1.71 V to 1.89 V	ROUT[11:0], HSYNC, VSYNC, LOCK, PASS	GND		0.45	V
V_IH	High Level Input Voltage	V_(VDDIO) = 1.71 V to 1.89 V		GPIO[3:0], PDB, OEN, SEL, OSS_SEL, BISTEN	0.65 × V_(VDDIO)		V_(VDDIO)	V
V_IL	Low Level Input Voltage	V_(VDDIO) = 1.71 V to 1.89 V		GPIO[3:0], PDB, OEN, SEL, OSS_SEL, BISTEN	GND		0.35 × V_(VDDIO)	V
I_IH	Input High Current	V_IN = 1.71 V to 1.89 V		GPIO[3:0]⁽⁴⁾, OEN	–20		20	μA
I_IH	Input High Current	V_IN = 1.71 V to 1.89 V		GPIO[2:0]⁽⁵⁾, SEL, PDB, OSS_SEL, BISTEN	–100		100	μA
I_IL	Input Low Current	V_IN = 0 V		GPIO[3:0], PDB, OEN, SEL, OSS_SEL, BISTEN	–20		20	μA
I_OS	Output Short Circuit Current	V_OUT = 0 V				–17		mA
I_OZ	TRI-STATE Output Current	V_OUT = 0 V or V_(VDDIO), PDB = L			–20		20	μA
3.3-V LVCMOS I/O⁽⁶⁾
V_OH	High Level Output Voltage	I_OH = –4 mA	V_(VDDIO) = 3.0 V to 3.6 V	GPIO[3:0], ROUT[11:0], HSYNC, VSYNC, LOCK, PASS	2.4		V_(VDDIO)	V
V_OL	Low Level Output Voltage	I_OL = 4 mA	V_(VDDIO) = 3.0 V to 3.6 V	GPIO[3:0], ROUT[11:0], HSYNC, VSYNC, LOCK, PASS	GND		0.4	V
V_IH	High Level Input Voltage	V_(VDDIO) = 3.0 V to 3.6 V		GPIO[3:0], OEN, SEL, OSS_SEL, BISTEN	2		V_(VDDIO)	V
V_IH	High Level Input Voltage	V_(VDDIO) = 3.0 V to 3.6 V		PDB	1.17		V_(VDDIO)	V
V_IL	Low Level Input Voltage	V_(VDDIO) = 3.0 V to 3.6 V		GPIO[3:0], OEN, SEL, OSS_SEL, BISTEN	GND		0.8	V
V_IL	Low Level Input Voltage	V_(VDDIO) = 3.0 V to 3.6 V		PDB	GND		0.63	V
I_IH	Input High Current	V_IN = 3.0 V to 3.6 V		GPIO[3:0]⁽⁴⁾, OEN, PDB	-20		20	μA
I_IH	Input High Current	V_IN = 3.0 V to 3.6 V		GPIO[2:0]⁽⁵⁾, SEL, OSS_SEL, BISTEN	–190		190	μA
I_IL	Input Low Current	V_IN = 0 V		GPIO[3:0], OEN, SEL, OSS_SEL, BISTEN, PDB	–20		20	μA
I_OS	Output Short Circuit Current	V_OUT = 0 V				–40		mA
I_OZ	TRI-STATE Output Current	V_OUT = 0 V or V_(VDDIO), PDB = LOW			–60		60	μA
I2C SERIAL CONTROL BUS⁽²⁾
V_IH	Input High Level			I2C_SDA, I2C_SCL	0.7 × V_(VDDIO)		V_(VDDIO)	V
V_IL	Input Low Level				GND		0.3 × V_(VDDIO)	V
V_HY	Input Hysteresis				50			mV
V_OL	Output Low Level	Standard/Fast Mode - I_OL = 4 mA; Fast Plus Mode - I_OL = 20 mA			0		0.4	V
I_IH	Input High Current	V_IN = V_(VDDIO)			–10		10	μA
I_IL	Input Low Current	V_IN = 0V			–10		10	μA
C_IN	Input Capacitance⁽³⁾					5	10	pF
FPD-LINK III INPUT
V_CM	Common Mode Voltage See Figure 4-2.					1.2		V
R_T	Internal Termination Resistor	Single Ended			40	50	60	?
R_T	Internal Termination Resistor	Differential			80	100	120	?
FPD-LINK III BIDIRECTIONAL CONTROL CHANNEL
V_OUT-BC	Back Channel Single-Ended Output Voltage	RL = 50 Ω, Coaxial configuration, forward channel disabled		RIN0+, RIN1+	190		260	mV
V_OD-BC	Back Channel Differential Output Voltage	RL = 100 Ω, STP configuration, forward channel disabled		RIN0+, RIN0– RIN1+, RIN1–	380		520	mV

(1) V_(VDDIO) = 1.8 V ± 5%

(2) V_(VDDIO) = 1.8 V ± 5% OR 3.0 V to 3.6 V

(3) Specification is ensured by design and/or characterization and is not tested in production.

(1) The back channel frequency (MHz) listed is the frequency of the internal clock used to generate the encoded back channel data stream. The data rate (Mbps) of the encoded back channel stream is the back channel frequency divided by 2.

(4) GPIO[2:0] Pulldown disabled; Register 0xBE = 0x03

(5) GPIO[2:0] Pulldown enabled; Register 0xBE = 0x00

(6) V_(VDDIO) = 3.0 V to 3.6 V