ZHCSG37C September 2016 – December 2022 DS90UB934-Q1
PRODUCTION DATA
- 特性
- 1應用
- 2說明
- 3Revision History
- Pin Configuration and Functions
- 4Specifications
-
5Detailed Description
- 5.1 Overview
- 5.2 Functional Block Diagram
- 5.3 Feature Description
- 5.4 Device Functional Modes
- 5.5 Programming
- 5.6 Register Maps
- 6Application and Implementation
- Mechanical, Packaging, and Orderable Information
- 7Device and Documentation Support
- Mechanical, Packaging, and Orderable Information
5.4.3 Input Jitter Tolerance
Input jitter tolerance is the ability of the CDR PLL of the receiver to track and recover the incoming serial data stream. Jitter tolerance at a specific frequency is the maximum jitter permissible before data errors occur. Figure 5-3 and Table 5-4 show the allowable total jitter of the receiver inputs and must be less than the values in Table 5-4.
Figure 5-3 Input Jitter Tolerance PlotTable 5-4 Input Jitter Tolerance Limit
| INTERFACE | JITTER AMPLITUDE (UI p-p) | FREQUENCY (MHz) (1) | ||
|---|---|---|---|---|
| FPD3 | A1 | A2 | ?1 | ?2 |
| 1 | 0.4 | FPD3_PCLK / 80 | FPD3_PCLK / 15 | |
(1) FPD3_PCLK is equivalent to PCLK frequency based on the operating MODE:
10-bit mode: PCLK_Freq. /2
12-bit HF mode: PCLK_Freq. x 2/3
12-bit LF mode: PCLK_Freq.
10-bit mode: PCLK_Freq. /2
12-bit HF mode: PCLK_Freq. x 2/3
12-bit LF mode: PCLK_Freq.