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ZHCSG37C September 2016 – December 2022 DS90UB934-Q1

PRODUCTION DATA

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

RGZ|48
- MPQF123F

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

RGZ|48
- QFND014T

訂購信息

4.6 AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER		TEST CONDITIONS	PIN OR FREQUENCY	MIN	TYP	MAX	UNIT
LVCMOS I/O
t_RCP	Receiver Output Clock Period. See Figure 4-7.	10-bit Mode	PCLK, 50 - 100 MHz	10		20	ns
		12-bit HF Mode	PCLK, 37.5 - 100 MHz	10		26.7
		12-bit LF Mode	PCLK, 25 - 50 MHz	20		40
t_PDC	PCLK Duty Cycle⁽¹⁾	10-bit Mode	PCLK	45%	50%	55%
t_PDC	PCLK Duty Cycle⁽¹⁾	12-bit HF or LF Mode	PCLK	40%	50%	60%
t_CLH	LVCMOS Low-to-High Transition Time⁽¹⁾ See Figure 4-1.	V_(VDDIO) = 1.71 V to 1.89 V OR V_(VDDIO) = 3.0 V to 3.6 V CL = 8 pF (lumped load) Default Registers	PCLK		2	2.8	ns
t_CHL	LVCMOS High-to-Low Transition Time⁽¹⁾ See Figure 4-1.		PCLK		2	2.8	ns
t_CLH	LVCMOS Low-to-High Transition Time⁽¹⁾ See Figure 4-1.		ROUT[11:0], HSYNC, VSYNC, GPIO[2:0]		2	3	ns
t_CHL	LVCMOS High-to-Low Transition Time⁽¹⁾ See Figure 4-1.		ROUT[11:0], HSYNC, VSYNC, GPIO[2:0]		2	3	ns
t_ROS	ROUT Setup Data to PCLK⁽¹⁾ See Figure 4-7.		PCLK, ROUT[11:0], HSYNC, VSYNC	0.38T	0.5T		ns
t_ROH	ROUT Hold Data to PCLK⁽¹⁾ See Figure 4-7.		PCLK, ROUT[11:0], HSYNC, VSYNC	0.38T	0.5T		ns
t_DD	Deserializer Delay⁽¹⁾ See Figure 4-6.	Default Registers (RRFB = 1)	10-bit mode	175T		185T	ns
			12-bit HF mode	100T		115T
			12-bit LF mode	65T		80T
t_DDLT	Deserializer Data Lock Time See Figure 4-3.	Digital Reset, or PDB = HIGH to LOCK = HIGH	10-bit mode			22	ms
			12-bit HF mode			22
			12-bit LF mode			22
t_RCJ	Receiver Clock Jitter⁽¹⁾	PCLK, SSCG[0] = OFF	10-bit mode		40	70	ps
			12-bit HF mode		52	90
			12-bit LF mode		45	85
t_DPJ	Deserializer Period Jitter⁽¹⁾	PCLK, SSCG[0] = OFF	10-bit mode		885	1020	ps
			12-bit HF mode		420	880
			12-bit LF mode		400	515
t_DCCJ	Deserializer Cycle-to-Cycle Clock Jitter⁽¹⁾⁽²⁾	PCLK, SSCG[0] = OFF	10-bit mode		1360	1800	ps
			12-bit HF mode		1280	1500
			12-bit LF mode		890	1150
f_dev	Spread Spectrum Clocking Deviation Frequency See Figure 4-9.	LVCMOS Output Bus, SSCG[0] = ON	25 - 100 MHz		±0.5% to ±2.5%
f_mod	Spread Spectrum Clocking Modulation Frequency See Figure 4-9.	LVCMOS Output Bus, SSCG[0] = ON	25 - 100 MHz		5 to 50		kHz
FPD-Link III
V_IN	Single Ended Input Voltage See Figure 4-2.	Coaxial configuration. 1010 pattern applied to the far end of a 15 meter cable. V_IN measured after the cable, at the deserializer input pins.			50		mV
V_ID	Differential Input Voltage See Figure 4-2.	STP Configuration. 1010 pattern applied to the far end of a 15 meter cable. V_ID measured after the cable, at the deserializer input pins.			100		mV
?_BC	Back Channel Frequency		RIN0+, RIN0– RIN1+, RIN1–	3.5		5.5	MHz
T_J	Back Channel Jitter⁽¹⁾				7	15	ns
T_IJIT	Input Jitter	10MHz Sinusoidal Jitter applied to FPD-Link III input				0.4	UI⁽³⁾

(1) Specification is ensured by design and/or characterization and is not tested in production.

(2) Specification is ensured by characterization

(3) 1UI = 1 bit time of FPD-Link Forward channel