ZHCSEP5D January 2016 – November 2018 DRV8884
PRODUCTION DATA.
The DRV8884 is active unless the nSLEEP pin is brought logic low. In sleep mode, the charge pump is disabled, the H-bridge FETs are disabled Hi-Z, and the V3P3 regulator is disabled. Note that tSLEEP must elapse after a falling edge on the nSLEEP pin before the device is in sleep mode. The DRV8884 is brought out of sleep mode automatically if nSLEEP is brought logic high. Note that tWAKE must elapse before the outputs change state after wake-up.
TI recommends to keep the STEP pin logic low when coming out of nSLEEP or when applying power.
If the ENABLE pin is brought logic low, the H-bridge outputs are disabled, but the internal logic will still be active. A rising edge on STEP will advance the indexer, but the outputs will not change state until ENABLE is asserted.
| CONDITION | H-BRIDGE | CHARGE PUMP | INDEXER | V3P3 | |
|---|---|---|---|---|---|
| Operating | 8 V < VM < 40 V
nSLEEP pin = 1 ENABLE pin = 1 |
Operating | Operating | Operating | Operating |
| Disabled | 8 V < VM < 40 V
nSLEEP pin = 1 ENABLE pin = 0 |
Disabled | Operating | Operating | Operating |
| Sleep mode | 8 V < VM < 40
nSLEEP pin = 0 |
Disabled | Disabled | Disabled | Disabled |
| Fault encountered | VM undervoltage (UVLO) | Disabled | Disabled | Disabled | Disabled |
| VCP undervoltage (CPUV) | Disabled | Operating | Operating | Operating | |
| Overcurrent (OCP) | Disabled | Operating | Operating | Operating | |
| Thermal shutdown (TSD) | Disabled | Operating | Operating | Operating | |