ZHCSEP5D January 2016 – November 2018 DRV8884
PRODUCTION DATA.
Figure 23 gives the input structure for logic-level pins STEP, DIR, ENABLE, nSLEEP, and M1.
Figure 23. Logic-level Input Pin Diagram Tri-level logic pins M0 and TRQ have the following structure shown in Figure 24.
Quad-level logic pin DECAY has the following structure shown in Figure 25.
Figure 25. Quad-level Input Pin Diagram