ZHCSEP5D January 2016 – November 2018 DRV8884
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Stepper Motor Driver Current Ratings
- 7.3.2 PWM Motor Drivers
- 7.3.3 Microstepping Indexer
- 7.3.4 Current Regulation
- 7.3.5 Controlling RREF With an MCU DAC
- 7.3.6 Decay Modes
- 7.3.7 Blanking Time
- 7.3.8 Charge Pump
- 7.3.9 LDO Voltage Regulator
- 7.3.10 Logic and Multi-Level Pin Diagrams
- 7.3.11 Protection Circuits
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
7.3.9 LDO Voltage Regulator
An LDO regulator is integrated into the DRV8884. DVDD can be used to provide a reference voltage. For proper operation, bypass DVDD to GND using a ceramic capacitor.
The DVDD output is nominally 3.3 V. When the DVDD LDO current load exceeds 1 mA, the output voltage drops significantly.
The AVDD pin also requires a bypass capacitor to GND. This LDO is for DRV8884 internal use only.
Figure 22. LDO Diagram If a digital input needs to be tied permanently high (that is, Mx, DECAY, or TRQ), it is preferable to tie the input to DVDD instead of an external regulator. This saves power when VM is not applied or in sleep mode; DVDD is disabled and current will not be flowing through the input pulldown resistors. For reference, logic level inputs have a typical pulldown of 100 kΩ, and tri-level inputs have a typical pulldown of 60 kΩ.