ZHCSG08E October 2016 – January 2021 DRV8702-Q1 , DRV8703-Q1
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
The DRV870x-Q1 device is active unless the nSLEEP pin is brought low. In sleep mode, the charge pump is disabled, the H-bridge FETs are disabled to the Hi-Z state, and the AVDD and DVDD regulators are disabled.
The t(SLEEP) time must elapse after a falling edge on the nSLEEP pin before the device is in sleep mode. The DRV870x-Q1 device is brought out of sleep mode automatically if the nSLEEP pin is brought high.
The t(WAKE) time must elapse before the outputs change state after wakeup.
On the DRV8703-Q1 device, the SPI settings are reset when coming out of UVLO or exiting sleep mode.
While the nSLEEP pin is brought low, all external H-bridge FETs are disabled. The high-side gate pins, GHx, are pulled to the output node, SHx, by an internal resistor and the low-side gate pins, GLx, are pulled to ground.
When the VM voltage is not applied and during the power-on time (ton) the outputs are disabled using weak pulldown resistors between the GHx and SHx pins and the GLx and GND pins.
The MODE pin controls the device-logic operation for phase and enable, independent half-bridge, or PWM input modes. This operation is latched on power up or when exiting sleep mode.