ZHCSG08E October 2016 – January 2021 DRV8702-Q1 , DRV8703-Q1
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| POWER SUPPLIES (VM, AVDD, DVDD) | ||||||
| t(SLEEP) | Sleep time | nSLEEP = low to sleep mode | 100 | μs | ||
| t(wu) | Wake-up time | nSLEEP = high to output change | 1 | ms | ||
| ton | Turn on time | VM > UVLO2 to output transition | 1 | ms | ||
| CHARGE PUMP (VCP, CPH, CPL) | ||||||
| fS(VCP) | Charge-pump switching frequency | VM > UVLO2 | 200 | 400 | 700 | kHz |
| CONTROL INPUTS (IN1, IN2, nSLEEP, MODE, nSCS, SCLK, SDI, PH, EN) | ||||||
| tpd | Propagation delay | IN1, IN2 to GHx or GLx | 500 | ns | ||
| FET GATE DRIVERS (GH1, GH2, SH1, SH2, GL1, GL2) | ||||||
| t(DEAD) | Output dead time (DRV8702-Q1) | Observed t(DEAD) depends on IDRIVE setting | 240 | ns | ||
| t(DEAD) | Output dead time (DRV8703-Q1) | TDEAD = 2’b00; Observed t(DEAD) depends on IDRIVE setting | 120 | ns | ||
| TDEAD = 2’b01; Observed t(DEAD) depends on IDRIVE setting | 240 | |||||
| TDEAD = 2’b10; Observed t(DEAD) depends on IDRIVE setting | 480 | |||||
| TDEAD = 2’b11; Observed t(DEAD) depends on IDRIVE setting | 960 | |||||
| t(DRIVE) | Gate drive time | 2.5 | μs | |||
| CURRENT SHUNT AMPLIFIER AND PWM CURRENT CONTROL (SP, SN, SO, VREF) | ||||||
| tS | Settling time to ±1%(1) | VSP = VSN = GND to VSP = 240 mV, VSN = GND, AV= 10; C(SO) = 200 pF | 0.5 | μs | ||
| VSP = VSN = GND to VSP = 120 mV, VSN = GND, AV= 20; C(SO) = 200 pF | 1 | |||||
| VSP = VSN = GND to VSP = 60 mV, VSN = GND, AV= 40; C(SO) = 200 pF | 2 | |||||
| VSP = VSN = GND to VSP = 30 mV, VSN = GND, AV= 80; C(SO) = 200 pF | 4 | |||||
| toff | PWM off-time (DRV8702-Q1) | 25 | μs | |||
| toff | PWM off-time (DRV8703-Q1) | TOFF = 00 | 25 | μs | ||
| TOFF = 01 | 50 | |||||
| TOFF = 10 | 100 | |||||
| TOFF = 11 | 200 | |||||
| t(BLANK) | PWM blanking time | 2 | μs | |||
| PROTECTION CIRCUITS | ||||||
| t(UVLO) | VM UVLO falling deglitch time | VM falling; UVLO report | 10 | μs | ||
| t(OCP) | Overcurrent deglitch time | 3.7 | 4 | 4.3 | μs | |
| t(RETRY) | Overcurrent retry time | 2.8 | 3 | 3.2 | ms | |
| t(WD) | Watchdog time out (DRV8703-Q1) | WD_DLY = 2’b00 | 10 | ms | ||
| WD_DLY = 2’b01 | 20 | |||||
| WD_DLY = 2’b10 | 50 | |||||
| WD_DLY = 2’b11 | 100 | |||||
| t(RESET) | Watchdog timer reset period | 64 | μs | |||
| SPI | ||||||
| t(SPI_READY) | SPI read after power on | VM > VUVLO1 | 5 | 10 | ms | |
| td(SDO) | SDO output data delay time, CLK high to SDO valid | CL = 20 pF | 30 | ns | ||
| ta | SCS access time, SCS low to SDO out of high impedance | 10 | ns | |||
| tdis | SCS disable time, SCS high to SDO high impedance | 10 | ns | |||