ZHCSND1A November 2020 – May 2022 DRV8434
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| POWER SUPPLIES (VM, DVDD) | ||||||
| IVM | VM operating supply current | ENABLE = 1, nSLEEP = 1, No motor load | 5 | 6.5 | mA | |
| IVMQ | VM sleep mode supply current | nSLEEP = 0 | 2 | 4 | μA | |
| tSLEEP | Sleep time | nSLEEP = 0 to sleep-mode |
120 |
μs | ||
| tRESET | nSLEEP reset pulse | nSLEEP low to clear fault |
20 |
40 |
μs | |
| tWAKE | Wake-up time | nSLEEP = 1 to output transition | 0.8 | 1.2 | ms | |
| tON | Turn-on time | VM > UVLO to output transition | 0.8 | 1.2 | ms | |
|
tEN |
Enable time |
ENABLE = 0/1 to output transition |
5 |
μs | ||
| VDVDD | Internal regulator voltage | No external load, 6 V < VVM < 48V |
4.75 | 5 | 5.25 | V |
| No external load, VVM = 4.5V |
4.2 |
4.35 |
V |
|||
| CHARGE PUMP (VCP, CPH, CPL) | ||||||
| VVCP | VCP operating voltage | 6 V < VVM < 48 V | VVM + 5 | V | ||
| f(VCP) | Charge pump switching frequency | VVM > UVLO; nSLEEP = 1 | 360 | kHz | ||
| LOGIC-LEVEL INPUTS (STEP, DIR, nSLEEP) | ||||||
| VIL | Input logic-low voltage | 0 | 0.6 | V | ||
| VIH | Input logic-high voltage | 1.5 | 5.5 | V | ||
| VHYS | Input logic hysteresis | 150 | mV | |||
| IIL | Input logic-low current | VIN = 0 V | –1 | 1 | μA | |
| IIH | Input logic-high current | VIN = 5 V | 100 | μA | ||
| TRI-LEVEL INPUTS (M0, DECAY0, DECAY1, ENABLE) | ||||||
| VI1 | Input logic-low voltage | Tied to GND | 0 | 0.6 | V | |
| VI2 | Input Hi-Z voltage | Hi-Z | 1.8 | 2 | 2.2 | V |
| VI3 | Input logic-high voltage | Tied to DVDD | 2.7 | 5.5 | V | |
| IO | Output pull-up current | 10 | μA | |||
| QUAD-LEVEL INPUTS (M1, TOFF) | ||||||
| VI1 | Input logic-low voltage | Tied to GND | 0 | 0.6 | V | |
| VI2 | 330k? ± 5% to GND | 1 | 1.25 | 1.4 | V | |
| VI3 | Input Hi-Z voltage | Hi-Z | 1.8 | 2 | 2.2 | V |
| VI4 | Input logic-high voltage | Tied to DVDD | 2.7 | 5.5 | V | |
| IIL | Output pull-up current | 10 | μA | |||
| CONTROL OUTPUTS (nFAULT) | ||||||
| VOL | Output logic-low voltage | IO = 5 mA | 0.5 | V | ||
| IOH | Output logic-high leakage | –1 | 1 | μA | ||
| MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2) | ||||||
| RDS(ON) | High-side FET on resistance | TJ = 25 °C, IO = -1 A | 165 | 200 | m? | |
| TJ = 125 °C, IO = -1 A | 250 | 300 | m? | |||
| TJ = 150 °C, IO = -1 A | 280 | 350 | m? | |||
| RDS(ON) | Low-side FET on resistance | TJ = 25 °C, IO = 1 A | 165 | 200 | m? | |
| TJ = 125 °C, IO = 1 A | 250 | 300 | m? | |||
| TJ = 150 °C, IO = 1 A | 280 | 350 | m? | |||
| tSR | Output slew rate | VVM = 24 V, IO = 1 A, Between 10% and 90% | 240 | V/μs | ||
| PWM CURRENT CONTROL (VREF) | ||||||
| KV | Transimpedance gain | VREF = 3.3 V | 1.254 | 1.32 | 1.386 | V/A |
| IVREF | VREF Leakage Current | VREF = 3.3 V |
8.25 |
μA | ||
| tOFF | PWM off-time | TOFF = 0 | 7 | μs | ||
| TOFF = 1 | 16 | |||||
| TOFF = Hi-Z | 24 | |||||
| TOFF = 330 kΩ to GND | 32 | |||||
| ΔITRIP | Current trip accuracy | 0.25 A < IO < 0.5 A | –12 | 12 | % | |
| 0.5 A < IO < 1 A | –6 |
6 |
||||
| 1 A < IO < 2.5 A | –4 |
4 |
||||
| IO,CH | AOUT and BOUT current matching | IO = 2.5 A | –2.5 | 2.5 | % | |
| PROTECTION CIRCUITS | ||||||
| VUVLO | VM UVLO lockout | VM falling, UVLO falling | 4.1 | 4.25 | 4.35 | V |
| VM rising, UVLO rising | 4.2 | 4.35 | 4.45 | |||
| VUVLO,HYS | Undervoltage hysteresis | Rising to falling threshold | 100 | mV | ||
| VCPUV | Charge pump undervoltage | VCP falling; CPUV report | VVM + 2 | V | ||
| IOCP | Overcurrent protection | Current through any FET | 4 | A | ||
| tOCP | Overcurrent deglitch time | 2 | μs | |||
| tRETRY | Overcurrent retry time | 4 | ms | |||
| tOL | Open load detection time | 50 | ms | |||
| IOL | Open load current threshold | 75 | mA | |||
| TOTSD | Thermal shutdown | Die temperature TJ | 150 | 165 | 180 | °C |
| THYS_OTSD | Thermal shutdown hysteresis | Die temperature TJ | 20 | °C | ||