ZHCSG01C February 2017 – August 2018 DRV8320 , DRV8320R , DRV8323 , DRV8323R
PRODUCTION DATA.
| PIN | TYPE(1) | DESCRIPTION | |||
|---|---|---|---|---|---|
| NAME | NO. | ||||
| DRV8320H | DRV8320S | ||||
| AGND | 23 | 23 | PWR | Device analog ground. Connect to system ground. | |
| CPH | 1 | 1 | PWR | Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins. | |
| CPL | 32 | 32 | PWR | Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins. | |
| DVDD | 24 | 24 | PWR | 3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins. This regulator can source up to 30 mA externally. | |
| ENABLE | 22 | 22 | I | Gate driver enable. When this pin is logic low the device goes to a low-power sleep mode. An 8 to 40-µs pulse can be used to reset fault conditions. | |
| GHA | 5 | 5 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. | |
| GHB | 12 | 12 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. | |
| GHC | 13 | 13 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. | |
| GLA | 7 | 7 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. | |
| GLB | 10 | 10 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. | |
| GLC | 15 | 15 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. | |
| IDRIVE | 19 | — | I | Gate drive output current setting. This pin is a 7 level input pin set by an external resistor. | |
| INHA | 25 | 25 | I | High-side gate driver control input. This pin controls the output of the high-side gate driver. | |
| INHB | 27 | 27 | I | High-side gate driver control input. This pin controls the output of the high-side gate driver. | |
| INHC | 29 | 29 | I | High-side gate driver control input. This pin controls the output of the high-side gate driver. | |
| INLA | 26 | 26 | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver. | |
| INLB | 28 | 28 | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver. | |
| INLC | 30 | 30 | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver. | |
| MODE | 18 | — | I | PWM input mode setting. This pin is a 4 level input pin set by an external resistor. | |
| NC | 21 | — | NC | No internal connection. This pin can be left floating or connected to system ground. | |
| nFAULT | 17 | 17 | OD | Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor. | |
| nSCS | — | 21 | I | Serial chip select. A logic low on this pin enables serial interface communication. | |
| PGND | 31 | 31 | PWR | Device power ground. Connect to system ground. | |
| SCLK | — | 20 | I | Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. | |
| SDI | — | 19 | I | Serial data input. Data is captured on the falling edge of the SCLK pin. | |
| SDO | — | 18 | OD | Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor. | |
| SHA | 6 | 6 | I | High-side source sense input. Connect to the high-side power MOSFET source. | |
| SHB | 11 | 11 | I | High-side source sense input. Connect to the high-side power MOSFET source. | |
| SHC | 14 | 14 | I | High-side source sense input. Connect to the high-side power MOSFET source. | |
| SLA | 8 | 8 | I | Low-side source sense input. Connect to the low-side power MOSFET source. | |
| SLB | 9 | 9 | I | Low-side source sense input. Connect to the low-side power MOSFET source. | |
| SLC | 16 | 16 | I | Low-side source sense input. Connect to the low-side power MOSFET source. | |
| VCP | 2 | 2 | PWR | Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins. | |
| VDRAIN | 4 | 4 | I | High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains. | |
| VDS | 20 | — | I | VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor. | |
| VM | 3 | 3 | PWR | Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and PGND pins. | |
| Thermal Pad | PWR | Must be connected to ground | |||
| PIN | TYPE(1) | DESCRIPTION | |||
|---|---|---|---|---|---|
| NAME | NO. | ||||
| DRV8320RH | DRV8320RS | ||||
| AGND | 26 | 26 | PWR | Device analog ground. Connect to system ground. | |
| BGND | 34 | 34 | PWR | Buck regulator ground. Connect to system ground. | |
| CB | 35 | 35 | PWR | Buck regulator bootstrap input. Connect a X5R or X7R, 0.1-µF, 16-V, capacitor between the CB and SW pins. | |
| CPH | 3 | 3 | PWR | Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins. | |
| CPL | 2 | 2 | PWR | Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins. | |
| DVDD | 27 | 27 | PWR | 3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins. This regulator can source up to 30 mA externally. | |
| ENABLE | 25 | 25 | I | Gate driver enable. When this pin is logic low the device goes to a low-power sleep mode. An 8 to 40-µs low pulse can be used to reset fault conditions. | |
| FB | 40 | 40 | I | Buck feedback input. A resistor divider from the buck post inductor output to this pin sets the buck output voltage. | |
| GHA | 7 | 7 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. | |
| GHB | 14 | 14 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. | |
| GHC | 15 | 15 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. | |
| GLA | 9 | 9 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. | |
| GLB | 12 | 12 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. | |
| GLC | 17 | 17 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. | |
| GND | 19 | 19 | PWR | Device ground. Connect to system ground. | |
| IDRIVE | 22 | — | I | Gate drive output current setting. This pin is a 7 level input pin set by an external resistor. | |
| INHA | 28 | 28 | I | High-side gate driver control input. This pin controls the output of the high-side gate driver. | |
| INHB | 30 | 30 | I | High-side gate driver control input. This pin controls the output of the high-side gate driver. | |
| INHC | 32 | 32 | I | High-side gate driver control input. This pin controls the output of the high-side gate driver. | |
| INLA | 29 | 29 | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver. | |
| INLB | 31 | 31 | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver. | |
| INLC | 33 | 33 | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver. | |
| MODE | 21 | — | I | PWM input mode setting. This pin is a 4 level input pin set by an external resistor. | |
| NC | 24 | — | NC | No internal connection. This pin can be left floating or connected to system ground. | |
| NC | 37 | 37 | NC | No internal connection. This pin can be left floating or connected to system ground. | |
| nFAULT | 20 | 20 | OD | Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor. | |
| nSCS | — | 24 | I | Serial chip select. A logic low on this pin enables serial interface communication. | |
| nSHDN | 39 | 39 | I | Buck shutdown input. Enable and disable input (high voltage tolerant). Internal pullup current source. Pull lower than 1.25 V to disable. Float to enable. Establish input undervoltage lockout with two resistor divider. | |
| PGND | 1 | 1 | PWR | Device power ground. Connect to system ground. | |
| SCLK | — | 23 | I | Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. | |
| SDI | — | 22 | I | Serial data input. Data is captured on the falling edge of the SCLK pin. | |
| SDO | — | 21 | OD | Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor. | |
| SHA | 8 | 8 | I | High-side source sense input. Connect to the high-side power MOSFET source. | |
| SHB | 13 | 13 | I | High-side source sense input. Connect to the high-side power MOSFET source. | |
| SHC | 16 | 16 | I | High-side source sense input. Connect to the high-side power MOSFET source. | |
| SLA | 10 | 10 | I | Low-side source sense input. Connect to the low-side power MOSFET source. | |
| SLB | 11 | 11 | I | Low-side source sense input. Connect to the low-side power MOSFET source. | |
| SLC | 18 | 18 | I | Low-side source sense input. Connect to the low-side power MOSFET source. | |
| SW | 36 | 36 | O | Buck switch node. Connect this pin to an inductor, diode, and the CB bootstrap capacitor. | |
| VCP | 4 | 4 | PWR | Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins. | |
| VDRAIN | 6 | 6 | I | High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains. | |
| VDS | 23 | — | I | VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor. | |
| VIN | 38 | 38 | PWR | Buck regulator power supply input. Place an X5R or X7R, VM-rated ceramic capacitor between the VIN and BGND pins. | |
| VM | 5 | 5 | PWR | Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and PGND pins. | |
| Thermal Pad | PWR | Must be connected to ground | |||
| PIN | TYPE(1) | DESCRIPTION | |||
|---|---|---|---|---|---|
| NAME | NO. | ||||
| DRV8323H | DRV8323S | ||||
| AGND | 32 | 32 | PWR | Device analog ground. Connect to system ground. | |
| CAL | 31 | 31 | I | Amplifier calibration input. Set logic high to internally short amplifier inputs and perform auto offset calibration. | |
| CPH | 2 | 2 | PWR | Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins. | |
| CPL | 1 | 1 | PWR | Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins. | |
| DVDD | 33 | 33 | PWR | R 3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins. This regulator can source up to 30 mA externally. | |
| ENABLE | 30 | 30 | I | Gate driver enable. When this pin is logic low the device goes to a low-power sleep mode. An 8 to 40-µs low pulse can be used to reset fault conditions. | |
| GAIN | 29 | — | I | Amplifier gain setting. The pin is a 4 level input pin set by an external resistor. | |
| GHA | 6 | 6 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. | |
| GHB | 15 | 15 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. | |
| GHC | 16 | 16 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. | |
| GLA | 8 | 8 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. | |
| GLB | 13 | 13 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. | |
| GLC | 18 | 18 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. | |
| IDRIVE | 27 | — | I | Gate drive output current setting. This pin is a 7 level input pin set by an external resistor. | |
| INHA | 34 | 34 | I | High-side gate driver control input. This pin controls the output of the high-side gate driver. | |
| INHB | 36 | 36 | I | High-side gate driver control input. This pin controls the output of the high-side gate driver. | |
| INHC | 38 | 38 | I | High-side gate driver control input. This pin controls the output of the high-side gate driver. | |
| INLA | 35 | 35 | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver. | |
| INLB | 37 | 37 | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver. | |
| INLC | 39 | 39 | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver. | |
| MODE | 26 | — | I | PWM input mode setting. This pin is a 4 level input pin set by an external resistor. | |
| nFAULT | 25 | 25 | OD | Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor. | |
| nSCS | — | 29 | I | Serial chip select. A logic low on this pin enables serial interface communication. | |
| PGND | 40 | 40 | PWR | Device power ground. Connect to system ground. | |
| SCLK | — | 28 | I | Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. | |
| SDI | — | 27 | I | Serial data input. Data is captured on the falling edge of the SCLK pin. | |
| SDO | — | 26 | OD | Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor. | |
| SHA | 7 | 7 | I | High-side source sense input. Connect to the high-side power MOSFET source. | |
| SHB | 14 | 14 | I | High-side source sense input. Connect to the high-side power MOSFET source. | |
| SHC | 17 | 17 | I | High-side source sense input. Connect to the high-side power MOSFET source. | |
| SNA | 10 | 10 | I | Current sense amplifier input. Connect to the low-side of the current shunt resistor. | |
| SNB | 11 | 11 | I | Current sense amplifier input. Connect to the low-side of the current shunt resistor. | |
| SNC | 20 | 20 | I | Current sense amplifier input. Connect to the low-side of the current shunt resistor. | |
| SOA | 23 | 23 | O | Current sense amplifier output. | |
| SOB | 22 | 22 | O | Current sense amplifier output. | |
| SOC | 21 | 21 | O | Current sense amplifier output. | |
| SPA | 9 | 9 | I | Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor. | |
| SPB | 12 | 12 | I | Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor. | |
| SPC | 19 | 19 | I | Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor. | |
| VCP | 3 | 3 | PWR | Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins. | |
| VDRAIN | 5 | 5 | I | High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains. | |
| VDS | 28 | — | I | VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor. | |
| VM | 4 | 4 | PWR | Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and PGND pins. | |
| VREF | 24 | 24 | PWR | Current sense amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the VREF and AGND pins. | |
| Thermal Pad | PWR | Must be connected to ground | |||
| PIN | TYPE(1) | DESCRIPTION | |||
|---|---|---|---|---|---|
| NAME | NO. | ||||
| DRV8323RH | DRV8323RS | ||||
| AGND | 35 | 35 | PWR | Device analog ground. Connect to system ground. | |
| BGND | 43 | 43 | PWR | Buck regulator ground. Connect to system ground. | |
| CAL | 34 | 34 | I | Amplifier calibration input. Set logic high to internally short amplifier inputs and perform auto offset calibration. | |
| CB | 44 | 44 | PWR | Buck regulator bootstrap input. Connect a X5R or X7R, 0.1-µF, 16-V, capacitor between the CB and SW pins. | |
| CPH | 4 | 4 | PWR | Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins. | |
| CPL | 3 | 3 | PWR | Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins. | |
| DGND | 27 | 27 | PWR | Device ground. Connect to system ground. | |
| DVDD | 36 | 36 | PWR | 3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins. This regulator can source up to 30 mA externally. | |
| ENABLE | 33 | 33 | I | Gate driver enable. When this pin is logic low the device goes to a low-power sleep mode. An 8 to 40-µs low pulse can be used to reset fault conditions. | |
| FB | 1 | 1 | I | Buck feedback input. A resistor divider from the buck post inductor output to this pin sets the buck output voltage. | |
| GAIN | 32 | — | I | Amplifier gain setting. The pin is a 4 level input pin set by an external resistor. | |
| GHA | 8 | 8 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. | |
| GHB | 17 | 17 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. | |
| GHC | 18 | 18 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. | |
| GLA | 10 | 10 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. | |
| GLB | 15 | 15 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. | |
| GLC | 20 | 20 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. | |
| IDRIVE | 30 | — | I | Gate drive output current setting. This pin is a 7 level input pin set by an external resistor. | |
| INHA | 37 | 37 | I | High-side gate driver control input. This pin controls the output of the high-side gate driver. | |
| INHB | 39 | 39 | I | High-side gate driver control input. This pin controls the output of the high-side gate driver. | |
| INHC | 41 | 41 | I | High-side gate driver control input. This pin controls the output of the high-side gate driver. | |
| INLA | 38 | 38 | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver. | |
| INLB | 40 | 40 | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver. | |
| INLC | 42 | 42 | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver. | |
| MODE | 29 | — | I | PWM input mode setting. This pin is a 4 level input pin set by an external resistor. | |
| NC | 46 | 46 | NC | No internal connection. This pin can be left floating or connected to system ground. | |
| nFAULT | 28 | 28 | OD | Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor. | |
| nSCS | — | 32 | I | Serial chip select. A logic low on this pin enables serial interface communication. | |
| nSHDN | 48 | 48 | I | Buck shutdown input. Enable and disable input (high voltage tolerant). Internal pullup current source. Pull lower than 1.25 V to disable. Float to enable. Establish input undervoltage lockout with two resistor divider. | |
| PGND | 2 | 2 | PWR | Device power ground. Connect to system ground. | |
| SCLK | — | 31 | I | Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. | |
| SDI | — | 30 | I | Serial data input. Data is captured on the falling edge of the SCLK pin. | |
| SDO | — | 29 | OD | Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor. | |
| SHA | 9 | 9 | I | High-side source sense input. Connect to the high-side power MOSFET source. | |
| SHB | 16 | 16 | I | High-side source sense input. Connect to the high-side power MOSFET source. | |
| SHC | 19 | 19 | I | High-side source sense input. Connect to the high-side power MOSFET source. | |
| SNA | 12 | 12 | I | Current sense amplifier input. Connect to the low-side of the current shunt resistor. | |
| SNB | 13 | 13 | I | Current sense amplifier input. Connect to the low-side of the current shunt resistor. | |
| SNC | 22 | 22 | I | Current sense amplifier input. Connect to the low-side of the current shunt resistor. | |
| SOA | 25 | 25 | O | Current sense amplifier output. | |
| SOB | 24 | 24 | O | Current sense amplifier output. | |
| SOC | 23 | 23 | O | Current sense amplifier output. | |
| SPA | 11 | 11 | I | Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor. | |
| SPB | 14 | 14 | I | Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor. | |
| SPC | 21 | 21 | I | Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor. | |
| SW | 45 | 45 | O | Buck switch node. Connect this pin to an inductor, diode, and the CB bootstrap capacitor. | |
| VCP | 5 | 5 | PWR | Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins. | |
| VDRAIN | 7 | 7 | I | High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains. | |
| VDS | 31 | — | I | VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor. | |
| VIN | 47 | 47 | PWR | Buck regulator power supply input. Place an X5R or X7R, VM-rated ceramic capacitor between the VIN and BGND pins. | |
| VM | 6 | 6 | PWR | Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and PGND pins. | |
| VREF | 26 | 26 | PWR | Current sense amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the VREF and AGND pins. | |
| Thermal Pad | PWR | Must be connected to ground | |||