ZHCSG01C February 2017 – August 2018 DRV8320 , DRV8320R , DRV8323 , DRV8323R
PRODUCTION DATA.
After a VDS_OCP event in this mode, all external MOSFETs are disabled and the nFAULT pin is driven low. When the external MOSFETs are disabled in this way, the driver automatically uses a lower setting for the gate drive current instead of the programmed IDRIVE setting. This setting lets any large current that may be present to be switched off slowly to minimize any inductive kickback caused by parasitic capacitance in the system. The FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal operation starts again (gate driver operation and the nFAULT pin is released) when the VDS_OCP condition clears and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).