ZHCSG01C February 2017 – August 2018 DRV8320 , DRV8320R , DRV8323 , DRV8323R
PRODUCTION DATA.
If at any time the voltage on the VCP pin (charge pump) falls lower than the VCPUV threshold voltage of the charge pump, all of the external MOSFETs are disabled and the nFAULT pin is driven low. The FAULT and CPUV bits are also latched high in the registers on SPI devices. Normal operation starts again (gate driver operation and the nFAULT pin is released) when the VCP undervoltage condition clears. The CPUV bit stays set until cleared through the CLR_FLT bit or an ENABLE pin reset pulse (tRST). Setting the DIS_CPUV bit high on the SPI devices disables this protection feature. On hardware interface devices, the CPUV protection is always enabled.