10 Revision History
Changes from Revision C (April 2024) to Revision D (June 2025)
- Added that JTAG_TDI/SD Pin is an active-low pin when the pin acts as the
signal detect pin. Added note to keep Hi-Z pins float/NC or connect to GND with 10kΩ
resistor.Go
- Changed Absolute Min from -0.3 to -0.5VGo
- Changed the terms "master" and "slave'" to "leader" and "follower" per the Texas
Instruments inclusive terminology standards
throughout documentGo
- Added
1000M to Link Loss Pass Through description
Go
- 4-Level
Strapping Mode 0 Rlo recommendation changed from 2.49k to
OPENGo
- Changed # to NumberGo
- LED1 default for opmode 001 and 010 changed from RX to TX.Go
- All instances of "master" and "slave" changed to "leader" and
"follower" respectively, Added fiber link status for register 18h LED
configurations (settings: 5h and 6h), Added Register Name for Register E9h,
Clarified Register 86h delay options, Clarified Register 170h[4:1] setting on
MAC impedance control, Clarified Register 1DFh[6] setting, Added Link Loss Pass
Through Enable Register (1ECh[3]). Removed Link Loss Pass Through No Link Bit
(1ECh[0]). Register C01h[2] clarified. Register C10h[9] clarified. Unreserved
register C1Ah[5] and register C30h[2]. Changed register D6h[14:13] bit name from
"SGMII_TESTMODE_SWING" to "SGMII_VOLTAGE_SWING"Go
- Added 25MHz Oscillator Phase Noise Figure.Go
- Added Section 8.2.1.2.1.3.Go
Changes from Revision B (December 2022) to Revision C (April 2024)
- RESET_N Pin State in IEEE PWDN corrected from PD to PUGo
- Added Junction Temperature SpecGo
- Magic Packet Detection Registers Table addedGo
- Added BIST Configuration exampleGo
- More detailed steps to enable MII mode of operation
addedGo
- Extended Register Space section formatted more
clearlyGo
- Corrected typo 100Base-T to 100Base-TXGo
- Corrected table functionsGo
- Added IPG Control Registers (0x7B-0x7C), SFD Registers (0xE9, 0x55),
PRBS Config Registers (0x71, 0x72, 0x1A8, 0x1A9), CLKOUT Config Reg (0xC6,
needed before writing to 0x170), and WoL Registers
(0x134-0x15F)Go
- Added RC ground isolation circuit to Magnetics connection figureGo
- Removed mention of SUPPLYMODE_SEL, pin 23, which doesn't exist on
this partGo
- Removed line mentioning SUPPLYMODE_SEL, does not exist on this
device.Go
Changes from Revision A (September 2018) to Revision B (December 2022)
- 更改了電流規格的光纖合規性Go
- 更新了整個文檔中的表格、圖和交叉參考的編號格式Go
- Deleted leading 0 from all register, read, and write statements Go
- Deleted 1000Base-X fiber application clarification, bug has been fixed Go
- Changed bridge mode image and description to clarify TX and RX pin behaviorGo
- Changed description of Media Converter mode to support Unmanaged
Media Converter mode in response to bug fix Go
- Changed register read and writes to correct values with comments Go
- Changed number of PHYs and size of PHY address to correct valuesGo
- Added clarification for Auto-Negotiation setting.Go
- Changed strapping modes in the figure and description to correct
valuesGo
- Changed Table 8-1 to
clarify Frequency Tolerance Go
- Changed to Table 8-2clarify Frequency Tolerance Go
- Changed the two-supply config figure to the correct number of pins for VDDIO and VDD1P1, also changed the pin name from VDDA1P1 to VDD1P1Go
- Changed the three-supply config figure to the correct number of pins
for VDDIO and VDD1P1, also changed the pin name from VDDA1P1 to
VDD1P1Go