5 Pin Configuration and Functions

DP83869HM RGZ
Package(48-Pin
VQFN)Top
View

Figure 5-1 RGZ Package
(48-Pin VQFN)
Top View

Table 5-1 RGZ Package (VQFN) Pin Functions

PIN		I/O	TYPE	DESCRIPTION
NO.	NAME	I/O	TYPE	DESCRIPTION
1	TD_P_A	I/O	Analog	Differential Transmit and Receive Signals
2	TD_M_A	I/O	Analog	Differential Transmit and Receive Signals
3	VDDA2P5	I	Power	2.5V Analog Supply (+/-5%). Each pin requires a 1μF and 0.1μF capacitor to GND.
4	TD_P_B	I/O	Analog	Differential Transmit and Receive Signals
5	TD_M_B	I/O	Analog	Differential Transmit and Receive Signals
6	VDD1P1	I	Power	1.1V Digital Supply (+/-10%). Each pin requires a 1μF and 0.1μF capacitor to GND.
7	TD_P_C	I/O	Analog	Differential Transmit and Receive Signals
8	TD_M_C	I/O	Analog	Differential Transmit and Receive Signals
9	VDDA2P5	I	Power	2.5V Analog Supply (+/-5%). Each pin requires a 1μF and 0.1μF capacitor to GND.
10	TD_P_D	I/O	Analog	Differential Transmit and Receive Signals
11	TD_M_D	I/O	Analog	Differential Transmit and Receive Signals
12	RBIAS	I	—	Bias Resistor Connection. An 11kΩ +/-1% resistor must be connected from RBIAS to GND.
13	VDDA1P8_1	I	Power	No external supply is required for this pin in two-supply mode. When unused, no connections can be made to these pins. In three-supply mode, an external 1.8V(+/-5%) supply can be connected to these pins. When using an external supply, each pin requires a 1μF and 0.1μF capacitor to GND.
14	SON	O	Analog	Differential SGMII or Fiber Data Output: This signal carries data from the PHY to the MAC, fiber transceiver, or link partner in SGMII and fiber modes. This pin is AC-coupled to the distant device through a 0.1μF capacitor. This pin provides LVDS signals, additional components can be required for the optical transceiver.
15	SOP	O	Analog	Differential SGMII or Fiber Data Output: This signal carries data from the PHY to the MAC, fiber transceiver, or link partner in SGMII and fiber modes. This pin is AC-coupled to the distant device through a 0.1μF capacitor. This pin provides LVDS signals, additional components can be required for the optical transceiver
16	SIP	I	Analog	Differential SGMII or Fiber Data Input: This signal carries data from the MAC, fiber transceiver, or link partner, to the PHY in SGMII and fiber modes. This pin is AC-coupled to the distant device through a 0.1μF capacitor. This pin accepts LVDS signals, additional components can be required for the optical transceiver
17	SIN	I	Analog	Differential SGMII or Fiber Data Input: This signal carries data from the MAC, fiber transceiver, or link partner, to the PHY in SGMII and fiber modes. This pin is AC-coupled to the distant device through a 0.1μF capacitor. This pin accepts LVDS signals, additional components can be required for the optical transceiver
18	VDDIO	I	Power	I/O Power: 1.8V (±5%), 2.5V (±5%) or 3.3V (±5%). Each pin requires a 1μF and 0.1μF capacitor to GND
19	XO	O	Clock	CRYSTAL OSCILLATOR OUTPUT: Second terminal for 25MHz crystal. Must be left floating if a clock oscillator is used.
20	XI	I	Clock	CRYSTAL OSCILLATOR INPUT: 25MHz oscillator or crystal input.
21	JTAG_CLK/TX_ER	I	WPU	JTAG TEST CLOCK: IEEE 1149.1 Test Clock input, primary clock source for all test logic input and output controlled by the testing entity. MII Mode: In MII mode, this pin is configured as TX_ER pin and is sourced from MAC to PHY. Use of this pin is optional.
22	JTAG_TDO/GPIO_1	O	—	JTAG TEST DATA OUTPUT: IEEE 1149.1 Test Data Output pin, the most recent test results are scanned out of the device via TDO. General Purpose I/O: This signal provides a multi-function configurable I/O. Please refer to the GPIO_MUX_CTRL register for details.
23	JTAG_TMS	I	WPU	JTAG TEST MODE SELECT: IEEE 1149.1 Test Mode Select pin, the TMS pin sequences the Tap Controller (16-state FSM) to select the desired test instruction. TI recommends applying 3 clock cycles with JTAG_TMS high to reset the JTAG.
24	JTAG_TDI/SD	I	WPU	JTAG TEST DATA INPUT: IEEE 1149.1 Test Data Input pin, test data is scanned into the device via TDI. SD: In 1000Base-X and 100Base-FX mode, this pin acts as Signal Detect. SD is an active low pin. This must be connected to Signal Detect of optical transceiver.
25	TX_D3	I	WPD	TRANSMIT DATA: Signal TX_D[3:0] carries data from the MAC to the PHY in RGMII mode and MII mode. Data is synchronous to the transmit clock. In RGMII mode GTX_CLK is the transmit clock and in MII mode TX_CLK is the transmit clock.
26	TX_D2	I	WPD
27	TX_D1	I	WPD
28	TX_D0	I	WPD
29	GTX_CLK/TX_CLK	I/O	WPD	RGMII TRANSMIT CLOCK: This continuous clock signal is sourced from the MAC layer to the PHY. Nominal frequency is 125MHz in 1000Mbps mode. This pin is Input in RGMII mode. MII TRANSMIT CLOCK: In MII mode, this pin provides a 25MHz reference clock for 100Mbps speed and a 2.5MHz reference clock for 10Mbps speed. This pin is output in MII mode. This pin is GTX_CLK by default and can be changed to TX_CLK by register configurations.
30	VDDIO	I	Power	I/O Power: 1.8V (±5%), 2.5V (±5%) or 3.3V (±5%). Each pin requires a 1μF and 0.1μF capacitor to GND
31	VDD1P1	I	Power	1.1V Digital Supply (+/-10%). Each pin requires a 1μF and 0.1μF capacitor to GND.
32	RX_CLK	O	Strap, WPD	RECEIVE CLOCK: Provides the recovered receive clocks for different modes of operation: 125MHz in 1000Mbps RGMII mode.
33	RX_D0	O	Strap, WPD	RECEIVE DATA: Signal RX_D[3:0] carries data from the PHY to the MAC in RGMII mode and in MII mode. Symbols received on the cable are decoded and presented on these pins synchronous to RX_CLK.
34	RX_D1	O	Strap, WPD
35	RX_D2	O	Strap, WPD
36	RX_D3	O	Strap, WPD
37	TX_CTRL/TX_EN	I	WPD	TRANSMIT CONTROL: In RGMII mode, TX_CTRL combines the transmit enable and the transmit error signal inputs from the MAC using both clock edges. TX_EN: In MII mode, this pin functions as TX_EN.
38	RX_CTRL/RX_DV	O	WPD	RECEIVE CONTROL: In RGMII mode, the receive data available and receive error are combined (RXDV_ER) using both rising and falling edges of the receive clock (RX_CLK). RX_DV: In MII mode, this pin functions as RX_DV.
39	VDD1P1	I	Power	1.1V Digital Supply (+/-10%). Each pin requires a 1μF and 0.1μF capacitor to GND.
40	CLK_OUT	O	Clock	CLOCK OUTPUT: Output clock
41	MDIO	I/O	—	MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that can be sourced by the management station or the PHY. This open-drain pin requires a 1.5kΩ pull-up resistor.
42	MDC	I	—	MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO serial management input/output data. This clock can be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 25MHz. There is no minimum clock rate.
43	RESET_N	I	—	RESET_N: This pin is an active-low reset input that initializes or re-initializes all the internal registers of the DP83869. Asserting this pin low for at least 1μs forces a reset process to occur. This pin is in IO voltage domain. A 100Ω resistor and 47uF capacitor are required to be connected in series between RESET_N pin and Ground.
44	INT_N/PWDN_N	I/O	—	INTERRUPT / POWER DOWN: The default function of this pin is POWER DOWN. POWER DOWN: This is an Active Low Input. Asserting this signal low enables the power-down mode of operation. In this mode the device powers down and consumes minimum power. Register access is available through the Management Interface to configure and power up the device. INTERRUPT: The interrupt pin is an open-drain, active low output signal indicating an interrupt condition has occurred. Register access is required to determine which event caused the interrupt. TI recommends using an external 2.2kΩ resistor connected to the VDDIO supply. When register access is disabled through pin option, the interrupt is asserted for 500ms before self-clearing.
45	LED_2/GPIO_0	I/O	Strap, WPD	LED_2: Part of VIO voltage domain. General Purpose I/O: This signal provides a multi-function configurable I/O. Please refer to the GPIO_MUX_CTRL register for details.
46	LED_1/RX_ER	O	Strap, WPD	LED_1: Part of VIO voltage domain. MII Mode: In MII mode this pin is configured as RX_ER. This pin is asserted high synchronously to rising edge of RX_CLK. Use of this pin is optional.
47	LED_0	O	Strap, WPD	LED_0: This pin is part of the VDDIO voltage domain
48	VDDA1P8_2	I	Power	No external supply is required for this pin in two-supply mode. When unused, no connections can be made to these pins. In three-supply mode, an external 1.8V(+/-5%) supply can be connected to these pins. When using an external supply, each pin requires a 1μF and 0.1μF capacitor to GND.

Pin Functionality definitions are given below:

I: Input
O: Output
I/O: Input/Output
Strap: Multifunctional bootstrap pins
WPD: Weak Pull Down Resistor (internal)
WPU: Weak Pull Up Resistor (internal)
Power: Power Supply Pins
Analog: Analog pins

Table 5-2 Pin States-1

PIN NO	PIN NAME	RESET		COPPER MODE
		RESET		MII		RGMII		SGMII
		PIN STATE	PULL/HI-Z	PIN STATE	PULL/HI-Z	PIN STATE	PULL/HI-Z	PIN STATE	PULL/HI-Z
14	SON	O	Hi-Z	O	Hi-Z	O	Hi-Z	O	50Ω
15	SOP	O	Hi-Z	O	Hi-Z	O	Hi-Z	O	50Ω
16	SIP	I	Hi-Z	I	Hi-Z	I	Hi-Z	I	50Ω
17	SIN	I	Hi-Z	I	Hi-Z	I	Hi-Z	I	50Ω
21	JTAG_CLK/ TX_ER	I	PU	I	PU	I	PU	I	PU
22	JTAG_TDO / GPIO_1	I	PD	O	Hi-Z	O	Hi-Z	O	Hi-Z
23	JTAG_TMS	I	PU	I	PU	I	PU	I	PU
24	JTAG_TDI / SD	I	PU	I	PU	I	PU	I	PU
25	TX_D3	I	PD	I	PD	I	PD	I	PD
26	TX_D2	I	PD	I	PD	I	PD	I	PD
27	TX_D1	I	PD	I	PD	I	PD	I	PD
28	TX_D0	I	PD	I	PD	I	PD	I	PD
29	GTX_CLK / TX_CLK	I	PD	O	PD	I	PD	I	PD
32	RX_CLK	I	PD	O	Hi-Z	O (125MHz)	Hi-Z	I	PD
33	RX_D0	I	PD	O	Hi-Z	O	Hi-Z	I	PD
34	RX_D1	I	PD	O	Hi-Z	O	Hi-Z	I	PD
35	RX_D2	I	PD	O	Hi-Z	O	Hi-Z	I	PD
36	RX_D3	I	PD	O	Hi-Z	O	Hi-Z	I	PD
37	TX_CTRL / TX_EN	I	PD	I	PD	I	PD	I	PD
38	RX_CTRL / RX_DV	I	PD	O	Hi-Z	O	Hi-Z	I	Hi-Z
40	CLK_OUT	O (25MHz)	Hi-Z	O (25MHz)	Hi-Z	O (25MHz)	Hi-Z	O (25MHz)	Hi-Z
41	MDIO	I	Hi-Z	I/O	Hi-Z	I/O	Hi-Z	I/O	Hi-Z
42	MDC	I	Hi-Z	I	Hi-Z	I	Hi-Z	I	Hi-Z
43	RESET_N	I	PU	I	PU	I	PU	I	PU
44	INT_N / PWDN_N	I	PU	I/O	PU/OD-PU	I/O	PU/OD-PU	I/O	PU/OD-PU
45	LED_2 / GPIO_0	I	PD	I/O	Hi-Z	I/O	Hi-Z	I/O	Hi-Z
46	LED_1 / RX_ER	I	PD	O	Hi-Z	O	Hi-Z	O	Hi-Z
47	LED_0	I	PD	O	Hi-Z	O	Hi-Z	O	Hi-Z

Table 5-3 Pin States-2

PIN NO	PIN NAME	MEDIA CONVERTOR		BRIDGE MODE
		MEDIA CONVERTOR		RGMII TO SGMII		SGMII TO RGMII
		PIN STATE	PULL/HI-Z	PIN STATE	PULL/HI-Z	PIN STATE	PULL/HI-Z
14	SON	O	50Ω	O	50Ω	O	50Ω
15	SOP	O	50Ω	O	50Ω	O	50Ω
16	SIP	I	50Ω	I	50Ω	I	50Ω
17	SIN	I	50Ω	I	50Ω	I	50Ω
21	JTAG_CLK/ TX_ER	I	PU	I	PU	I	PU
22	JTAG_TDO / GPIO_1	O	Hi-Z	O	Hi-Z	O	Hi-Z
23	JTAG_TMS	I	PU	I	PU	I	PU
24	JTAG_TDI / SD	I	PU	I	PU	I	PU
25	TX_D3	I	PD	I	PD	I	PD
26	TX_D2	I	PD	I	PD	I	PD
27	TX_D1	I	PD	I	PD	I	PD
28	TX_D0	I	PD	I	PD	I	PD
29	GTX_CLK / TX_CLK	I	PD	I	PD	I	PD
32	RX_CLK	I	PD	O	Hi-Z	O	Hi-Z
33	RX_D0	I	PD	O	Hi-Z	O	Hi-Z
34	RX_D1	I	PD	O	Hi-Z	O	Hi-Z
36	RX_D2	I	PD	O	Hi-Z	O	Hi-Z
36	RX_D3	I	PD	O	Hi-Z	O	Hi-Z
37	TX_CTRL / TX_EN	I	PD	I	PD	I	PD
38	RX_CTRL / RX_DV	I	PD	O	Hi-Z	O	Hi-Z
40	CLK_OUT	O (25MHz)	Hi-Z	O (25MHz)	Hi-Z	O (25MHz)	Hi-Z
41	MDIO	I/O	Hi-Z	I/O	Hi-Z	I/O	Hi-Z
42	MDC	I	Hi-Z	I	Hi-Z	I	Hi-Z
43	RESET_N	I	PU	I	PU	I	PU
44	INT_N / PWDN_N	I/O	PU/OD-PU	I/O	PU/OD-PU	I/O	PU/OD-PU
45	LED_2 / GPIO_0	I/O	Hi-Z	I/O	Hi-Z	I/O	Hi-Z
46	LED_1 / RX_ER	O	Hi-Z	O	Hi-Z	O	Hi-Z
47	LED_0	O	Hi-Z	O	Hi-Z	O	Hi-Z

Table 5-4 Pin States-3

PIN NO	PIN NAME	IEEE PWDN		MII ISOLATE
PIN NO	PIN NAME	PIN STATE	PULL/HI-Z	PIN STATE	PULL/HI-Z
14	SON	O	50Ω	O	50Ω
15	SOP	O	50Ω	O	50Ω
16	SIP	I	50Ω	I	50Ω
17	SIN	I	50Ω	I	50Ω
21	JTAG_CLK/ TX_ER	I/O	PU	I	PU
22	JTAG_TDO / GPIO_1	O	Hi-Z	O	Hi-Z
23	JTAG_TMS	I	PU	I	PU
24	JTAG_TDI / SD	I	PU	I	PU
25	TX_D3	I	PD	I	PD
26	TX_D2	I	PD	I	PD
27	TX_D1	I	PD	I	PD
28	TX_D0	I	PD	I	PD
29	GTX_CLK / TX_CLK	I	PD	I	PD
32	RX_CLK	O (2.5MHz)	Hi-Z	I	PD
33	RX_D0	O	Hi-Z	I	PD
34	RX_D1	O	Hi-Z	I	PD
36	RX_D2	O	Hi-Z	I	PD
36	RX_D3	O	Hi-Z	I	PD
37	TX_CTRL / TX_EN	I	PD	I	PD
38	RX_CTRL / RX_DV	O	Hi-Z	I	PD
40	CLK_OUT	O (25MHz)	Hi-Z	O (25MHz)	Hi-Z
41	MDIO	I	Hi-Z	I	Hi-Z
42	MDC	I	Hi-Z	I	Hi-Z
43	RESET_N	I	PU	I	PU
44	INT_N / PWDN_N	I/O	PU/OD-PU	I/O	PU/OD-PU
45	LED_2 / GPIO_0	O	Hi-Z	O	Hi-Z
46	LED_1 / RX_ER	O	Hi-Z	O	Hi-Z
47	LED_0	O	Hi-Z	O	Hi-Z

Note: Please leave Hi-Z pins floating or NC. If needed, please connect Hi-Z pins to GND with 10kΩ pull-down resistor.