ZHCSIS3D September 2018 – June 2025 DP83869HM
PRODUCTION DATA
When the DP83869HM is operating in 1000Mb leader mode, variation of the RX_SFD pulse can be estimated using the Skew FIFO Status register (register address 55h) bit[7:4]. The value read from the Skew FIFO Status register bit[7:4] must be multiplied by 8ns to estimate the RX_SFD variation added to the baseline latency.
Example: While operating in leader 1000Mb mode, a value of 0x2 is read from the Skew FIFO register bit[7:4].
2 × 8ns = 16ns is subtracted from the TX_SFD to RX_SFD measurement to determine the baseline latency.