ZHCSSP1 july 2023 BQ25173-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DRC|10
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DRC|10
訂購信息
5 Pin Configuration and Functions
Figure 5-1 DRC VSON Package 10-Pin (Top View)
Table 5-1 Pin Functions
| PIN | I/O(1) | DESCRIPTION | |
|---|---|---|---|
| NAME |
NO. |
||
|
IN |
1 | P | Input power. Connect to external DC supply. Bypass IN with at least 1-μF capacitor to GND, placed close to the IC. |
|
ISET |
2 |
I |
Programs the device fast-charge current, ICHG. External resistor from ISET to GND defines fast-charge current value. Expected range is 30 k? (10 mA) to 375 ? (800 mA). ICHG = KISET / RISET. |
| CE | 3 | I | Active low charge enable pin. Charging is enabled when CE pin is low. IC remains in Shutdown mode and charging is disabled when CE pin is high. An internal pulldown resistor (RPD_CE) enables the IC by default if this pin is floating. |
| NC | 4 | - | No connect pin, leave floating |
| GND | 5 | – | Ground pin |
| NC | 6 | - | No connect pin, leave floating |
| STAT | 7 | O | Open-drain charger status indication output. Connect to pullup rail with a 10-kΩ resistor. LOW indicates VOUT has reached 98% of the programmable regulation voltage, VREG. HIGH indicates charge in progress. |
| PG | 8 | O | Open-drain charger power-good output. Connect to pullup rail with a 10-kΩ resistor. PG goes LOW when VIN > VIN_LOWV and VOUT + VSLEEPZ < VIN < VIN_OV. |
| FB | 9 | I | Programs the supercapacitor regulation voltage, VREG. Use a feedback divider not exceeding 1 MΩ from VOUT to GND to set the regulation voltage. The bottom of the resistor divider network can be connected to PG for reduced power consumption when the input is removed (for VREG ≤ 5 V). |
| OUT | 10 | P | Supercapacitor connection. System load may be connected in parallel with supercapacitor. Bypass OUT with at least 1-μF capacitor to GND, placed close to the IC. |
| Thermal Pad | — | P | Exposed pad beneath the IC for heat dissipation. Solder thermal pad to the board with vias connecting to solid GND plane. |
(1) I = Input, O = Output, P = Power