SLUUD50 October 2024 BQ27Z758
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SLEEP | XCHG | XDSG | PF | SS | SDV | SEC1 | SEC0 | BTP_ INT | SHELF | RSVD | SHIP | ZVCHG | CHG | DSG | SHIPV |
| SLEEP (Bit 15): SLEEP mode conditions met | ||
| 1 = | Active | |
| 0 = | Inactive | |
| XCHG (Bit 14): Charging disabled | ||
| 0 = | Inactive | |
| 1 = | Active | |
| XDSG (Bit 13): Discharging disabled | ||
| 1 = | Active | |
| 0 = | Inactive | |
PF (Bit 12): PERMANENT FAILURE mode status | ||
1 = | Active | |
0 = | Inactive | |
| SS (Bit 11): SAFETY status. This is the ORd value of all the Safety Status bits. | ||
| 1 = | Active | |
| 0 = | Inactive | |
| SDV (Bit 10): SHUTDOWN mode triggered from a low cell voltage | ||
| 1 = | Active | |
| 0 = | Inactive | |
| SEC1, SEC0 (Bits 9, 8): SECURITY mode | ||
| 0, 0 = | Reserved | |
| 0, 1 = | Full Access | |
| 1, 0 = | Unsealed | |
| 1, 1 = | Sealed | |
| BTP_INT (Bit 7): Battery Trip Point Interrupt. Setting and clearing this bit depends on various conditions. | ||
| See Section 8.11 for details. | ||
| SHELF (Bit 6): SHELF mode | ||
| 1 = | Active | |
| 0 = | Inactive | |
| RSVD (Bit 5): Reserved | ||
| SHIP (Bit 4): SHIP mode | ||
| 1 = | Active | |
| 0 = | Inactive | |
| ZVCHG (Bit 3): Zero-volt (low voltage) charging status | ||
| 1 = | Active | |
| 0 = | Inactive | |
| CHG (Bit 2): CHG FET status | ||
| 1 = | Active | |
| 0 = | Inactive | |
| DSG (Bit 1): DSG FET status | ||
| 1 = | Active | |
| 0 = | Inactive | |
| SHIPV (Bit 0): SHIP mode triggered via low cell voltage | ||
| 1 = | Active | |
| 0 = | Inactive | |