SLUUCO9A April 2023 – November 2023 BQ28Z620
A write to this register is identical to writing to MACSubcmd(). For a description of MAC subcommands, see Section 14.2.
A read on this register returns the Control bits.
This Control Register is an I2C register, and the control bits are read back on register 0x00/0x01. These control bits are provided for backward compatibility and ease-of-use.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD | SEC1 | SEC0 | AUTHCALM | RSVD | RSVD | CheckSum Valid |
RSVD | RSVD | RSVD | RSVD | RSVD | LDMD | R_DIS | VOK | QMax |
| RSVD (Bit 15): Reserved | ||
| SEC1, SEC0 (Bits 14, 13): SECURITY mode | ||
| 0, 0 = | Reserved | |
| 0, 1 = | Full Access | |
| 1, 0 = | Unsealed | |
| 1, 1 = | Sealed | |
| AUTHCALM (Bit 12): Automatic CALIBRATION mode | ||
| 1 = | Enabled | |
| 0 = | Disabled | |
| RSVD (Bits 11–10): Reserved | ||
| CheckSumValid (Bit 9): Checksum is valid. | ||
| 1 = | Flash Writes are enabled. | |
| 0 = | Flash Writes are disabled due to low voltage or PF condition. | |
| RSVD (Bit 8–7): Reserved | ||
| RSVD (Bits 6–4): Reserved | ||
| LDMD (Bit 3): LOAD mode | ||
| 1 = | Constant oower | |
| 0 = | Constant current | |
| R_DIS (Bit 2): Resistance updates | ||
| 1 = | Disabled | |
| 0 = | Enabled | |
| VOK (Bit 1): Voltage OK for QMax updates | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| QMax (Bit 0): QMax updates. This bit toggles after every QMax update. | ||