ZHCSKC0 October 2019 UCC21736-Q1
ADVANCE INFORMATION for pre-production products; subject to change without notice.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
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6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Power Ratings
- 6.6 Electrical Characteristics
- 6.7 Switching Characteristics
- 6.8 Insulation Specifications
- 6.9 Safety-Related Certifications
- 6.10 Safety Limiting Values
- 6.11 Insulation Characteristics Curves
- 6.12 Typical Characteristics
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Power Supply
- 8.3.2 Driver Stage
- 8.3.3 VCC, VDD and VEE Undervoltage Lockout (UVLO)
- 8.3.4 Active Pulldown
- 8.3.5 Short Circuit Clamping
- 8.3.6 External Active Miller Clamp
- 8.3.7 Overcurrent and Short Circuit Protection
- 8.3.8 Fault (FLT, Reset and Enable (RST/EN)
- 8.3.9 ASC Protection and APWM Monitor
- 8.4 Device Functional Modes
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9 Applications and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Input filters for IN+, IN- and RST/EN
- 9.2.2.2 PWM Interlock of IN+ and IN-
- 9.2.2.3 FLT, RDY and RST/EN Pin Circuitry
- 9.2.2.4 RST/EN Pin Control
- 9.2.2.5 Turn on and turn off gate resistors
- 9.2.2.6 External Active Miller Clamp
- 9.2.2.7 Overcurrent and Short Circuit Protection
- 9.2.2.8 Higher Output Current Using an External Current Buffer
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
8.3.2 Driver Stage
UCC21736-Q1 has ±10A peak drive strength and is suitable for high power applications. The high drive strength can drive a SiC MOSFET module, IGBT module or paralleled discrete devices directly without extra buffer stage. UCC21736-Q1 can also be used to drive higher power modules or parallel modules with extra buffer stage. Regardless of the values of VDD, the peak sink and source current can be kept at 10A. The driver features an important safety function wherein, when the input pins are in floating condition, the OUTH/OUTL is held in LOW state. The split output of the driver stage is depicted in . The driver has rail-to-rail output by implementing a hybrid pull-up structure with a P-Channel MOSFET in parallel with an N-Channel MOSFET, and an N-Channel MOSFET to pulldown. The pull-up NMOS is the same as the pull down NMOS, so the on resistance RNMOS is the same as ROL. The hybrid pull-up structure delivers the highest peak-source current when it is most needed, during the miller plateau region of the power semiconductor turn-on transient. The ROH in represents the on-resistance of the pull-up P-Channel MOSFET. However, the effective pull-up resistance is much smaller than ROH. Since the pull-up N-Channel MOSFET has much smaller on-resistance than the P-Channel MOSFET, the pull-up N-Channel MOSFET dominates most of the turn-on transient, until the voltage on OUTH pin is about 3V below VDD voltage. The effective resistance of the hybrid pull-up structure during this period is about 2 x ROL . Then the P-Channel MOSFET pulls up the OUTH voltage to VDD rail. The low pull-up impedance results in strong drive strength during the turn-on transient, which shortens the charging time of the input capacitance of the power semiconductor and reduces the turn on switching loss.
The pull-down structure of the driver stage is implemented solely by a pull-down N-Channel MOSFET. The on-resistance of the N-Channel MOSFET ROL can be found in the . This MOSFET can ensure the OUTL voltage be pulled down to VEE rail. The low pull-down impedance not only results in high sink current to reduce the turn-off time, but also helps to increase the noise immunity considering the miller effect.
Figure 39. Gate Driver Output Stage