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ZHCSKC0 October 2019 UCC21736-Q1

ADVANCE INFORMATION for pre-production products; subject to change without notice.

封裝選項

機械數據 (封裝 | 引腳)

DW|16
- MSOI003I

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

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6.6 Electrical Characteristics

VCC=3.3V or 5.0V, 1uF capacitor from VCC to GND, VDD–COM=20V, 18V or 15V, COM–VEE =0V, 5V, 8V or 15V, C_L=100pF, –40°C<T_J<150°C (unless otherwise noted)⁽¹⁾⁽²⁾.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
VCC UVLO THRESHOLD AND DELAY
V_{VCC_ON}	VCC–GND		2.55	2.7	2.85	V
V_{VCC_OFF}			2.35	2.5	2.65
V_{VCC_HYS}				0.2
t_VCCFIL	VCC UVLO Deglitch time			10		µs
t_{VCC+ to OUT}	VCC UVLO on delay to output high	IN+ = VCC, IN– = GND		37.8
t_{VCC– to OUT}	VCC UVLO off delay to output low	IN+ = VCC, IN– = GND		10
t_{VCC+ to RDY}	VCC UVLO on delay to RDY high	RST/EN = VCC		37.8
t_{VCC– to RDY}	VCC UVLO off delay to RDY low	RST/EN = VCC		10
VDD UVLO THRESHOLD AND DELAY
V_{VDD_ON}	VDD–COM		11.2	12.0	12.8	V
V_{VDD_OFF}			9.9	10.7	11.5
V_{VDD_HYS}				0.8
t_VDDFIL	VDD UVLO Deglitch time			5		µs
t_{VDD+ to OUT}	VDD UVLO on delay to output high	IN+ = VCC, IN– = GND		5
t_{VDD– to OUT}	VDD UVLO off delay to output low	IN+ = VCC, IN– = GND		5
t_{VDD+ to RDY}	VDD UVLO on delay to RDY high	RST/EN = FLT=High		10
t_{VDD– to RDY}	VDD UVLO off delay to RDY low	RST/EN = FLT=High		10
VEE UVLO THRESHOLD AND DELAY
V_{VEE_ON}	VEE–COM		–3.3	–3.0	–2.7	V
V_{VEE_OFF}			–2.9	–2.6	–2.3
V_{VEE_HYS}				0.4
t_VEEFIL	VEE UVLO Deglitch time			5		µs
t_{VEE+ to OUT}	VEE UVLO on delay to output high	IN+ = VCC, IN– = GND		5
t_{VEE– to OUT}	VEE UVLO off delay to output low	IN+ = VCC, IN– = GND		5
t_{VEE+ to RDY}	VEE UVLO on delay to RDY high	RST/EN = FLT=High		10
t_{VEE– to RDY}	VEE UVLO off delay to RDY low	RST/EN = FLT=High		10
VCC, VDD QUIESCENT CURRENT
I_VCCQ	VCC quiescent current	OUT(H) = High, f_S = 0Hz, AIN=2V		3		mA
I_VCCQ	VCC quiescent current	OUT(L) = Low, f_S = 0Hz, AIN=2V		2		mA
I_VDDQ	VDD quiescent current	OUT(H) = High, f_S = 0Hz, AIN=2V		4		mA
I_VDDQ	VDD quiescent current	OUT(L) = Low, f_S = 0Hz, AIN=2V		3.7		mA
LOGIC INPUTS — IN+, IN–, and RST/EN
V_INH	Input high threshold	V_CC=3.3V		1.85	2.31	V
V_INL	Input low threshold	V_CC=3.3V	0.99	1.52		V
V_INHYS	Input threshold hysteresis	V_CC=3.3V		0.33		V
I_IH	Input high level input leakage current	V_IN = VCC		90		µA
I_IL	Input low level input leakage	V_IN = GND		–90		µA
R_IND	Input pins pull down resistance	see Detailed Description for more information		55		kΩ
R_INU	Input pins pull up resistance	see Detailed Description for more information		55		kΩ
T_INFIL	IN+, IN– and RST/EN deglitch (ON and OFF) filter time	f_S = 50kHz	28	40		ns
T_RSTFIL	Deglitch filter time to reset /FLT		500	650	800	ns
GATE DRIVER STAGE
I_OUT, I_OUTH	Peak source current	C_L=0.18µF, f_S=1kHz		–10		A
I_OUT, I_OUTL	Peak sink current	C_L=0.18µF, f_S=1kHz		10		A
R_OUTH	Output pull-up resistance	I_OUT = –0.1A		2.5		Ω
R_OUTL	Output pull-down resistance	I_OUT = 0.1A		0.3		Ω
V_OUTH	High level output voltage	I_OUT = –0.2A, V_DD=15V		14.5		V
V_OUTL	Low level output voltage	I_OUT = 0.2A		60		mV
ACTIVE PULLDOWN
V_OUTPD	Output active pull down on OUT, OUTL	I_OUTL or I_OUT = 0.1×I_OUT(L)(tpy), VDD=OPEN, VEE=COM			2.5	V
EXTERNAL MILLER CLAMP
V_CLMPTH	Miller clamp threshold voltage	Reference to VEE	1.5	2.0	2.5	V
V_CLMPE	Output high voltage	Reference to VEE	4.4	4.8		V
I_CLMPEH	Peak source current	C_CLMPE = 10nF	0.12	0.25		A
I_CLMPEL	Peak sink current	C_CLMPE = 10nF	0.12	0.25		A
t_CLMPER	Rising time	C_CLMPE = 330pF		20	40	ns
t_DCLMPE	Miller clamp ON delay time	C_CLMPE = 330pF		40		ns
SHORT CIRCUIT CLAMPING
V_CLP-OUT(H)	V_OUT–VDD, V_OUTH–VDD	OUT = Low, I_OUT(H) = 500mA, t_CLP=10us		0.9		V
V_CLP-OUT(L)	V_OUT–VDD, V_OUTL–VDD	OUT = High, I_OUT(L) = 500mA, t_CLP=10us		1.8		V
V_CLP-CLMPI	V_CLMPI–VDD	OUT = High, I_CLMPI = -20mA, t_CLP=10us		1.0		V
OC PROTECTION
I_DCHG	OC pull down current when	V_OC = 1V		40		mA
V_OCTH	Detection Threshold		0.63	0.7	0.77	V
V_OCL	Voltage when OUT(L) = LOW, Reference to COM	I_OC = 5mA		0.13		V
t_OCFIL	OC fault deglitch filter			150		ns
t_OCOFF	OC propagation delay to OUT(L) 90%			200		ns
t_OCFLT	OC to FLT low delay			600		ns
INTERNAL SOFT TURN-OFF
I_STO	Soft turn-off current on fault conditions			900		mA
ASC - Active Short Circuit
V_ASCL	ASC Input low threshold			1.7		V
V_ASCH	ASC Input high threshold			3.2		V
t_{ASC_r}	ASC to output rising edge delay			660		ns
t_{ASC_f}	ASC to output falling edge delay			227		ns
ISOLATED ASC MONITOR (APWM)
f_APWM	APWM output frequency		360	400	440	kHz
D_APWM	APWM Dutycycle —	V_ASC = 0.5V	7	10	13	%
		V_ASC = 2.5V	47	50	53
		V_ASC = 4.5V	87	90	93
FLT AND RDY REPORTING
t_RDYHLD	VDD UVLO RDY low minimum holding time		0.55		1	ms
t_FLTMUTE	Output mute time on fault	Reset fault through RST/EN	0.55		1	ms
R_ODON	Open drain output on resistance	I_ODON = 5mA		30		Ω
V_ODL	Open drain low output voltage	IODON = 5mA			0.3	V
COMMON MODE TRANSIENT IMMUNITY
CMTI	Common-mode transient immunity		150			V/ns

(1) Current are positive into and negative out of the specified terminal.

(2) All voltages are referenced to COM unless otherwise notified.