国产精品香蕉在线观看首页,成人国产一区二区三区精品,国产精品野外a∨久久久

ZHCSJR4D January 2019 – June 2024 UCC21710-Q1

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

DW|16
- MSOI003I

散熱焊盤機械數據 (封裝 | 引腳)

DW|16
- QFND505A

訂購信息

5.9 Electrical Characteristics

VCC=3.3V or 5.0V, 1uF capacitor from VCC to GND, VDD–COM=20V, 18V or 15V, COM–VEE =0V, 5V, 8V or 15V, C_L=100pF, –40°C<T_J<150°C (unless otherwise noted)⁽¹⁾⁽²⁾.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
VCC UVLO THRESHOLD AND DELAY
V_{VCC_ON}	VCC–GND		2.55	2.7	2.85	V
V_{VCC_OFF}			2.35	2.5	2.65
V_{VCC_HYS}				0.2
t_VCCFIL	VCC UVLO Deglitch time			10		μs
t_{VCC+ to OUT}	VCC UVLO on delay to output high	IN+ = VCC, IN– = GND	28	37.8	50
t_{VCC– to OUT}	VCC UVLO off delay to output low	IN+ = VCC, IN– = GND	5	10	15
t_{VCC+ to RDY}	VCC UVLO on delay to RDY high	RST/EN = VCC	30	37.8	50
t_{VCC– to RDY}	VCC UVLO off delay to RDY low	RST/EN = VCC	5	10	15
VDD UVLO THRESHOLD AND DELAY
V_{VDD_ON}	VDD–COM		10.5	12.0	12.8	V
V_{VDD_OFF}			9.9	10.7	11.8
V_{VDD_HYS}				0.8
t_VDDFIL	VDD UVLO Deglitch time			5		μs
t_{VDD+ to OUT}	VDD UVLO on delay to output high	IN+ = VCC, IN– = GND	2	5	8
t_{VDD– to OUT}	VDD UVLO off delay to output low	IN+ = VCC, IN– = GND		5	10
t_{VDD+ to RDY}	VDD UVLO on delay to RDY high	RST/EN = FLT=High		10	15
t_{VDD– to RDY}	VDD UVLO off delay to RDY low	RST/EN = FLT=High		10	15
VCC, VDD QUIESCENT CURRENT
I_VCCQ	VCC quiescent current	OUT(H) = High, f_S = 0Hz, AIN=2V	2.5	3	4	mA
I_VCCQ	VCC quiescent current	OUT(L) = Low, f_S = 0Hz, AIN=2V	1.45	2	2.75	mA
I_VDDQ	VDD quiescent current	OUT(H) = High, f_S = 0Hz, AIN=2V	3.6	4	5.9	mA
I_VDDQ	VDD quiescent current	OUT(L) = Low, f_S = 0Hz, AIN=2V	3.1	3.7	5.3	mA
LOGIC INPUTS — IN+, IN– and RST/EN
V_INH	Input high threshold	V_CC=3.3V		1.85	2.31	V
V_INL	Input low threshold	V_CC=3.3V	0.99	1.52		V
V_INHYS	Input threshold hysteresis	V_CC=3.3V		0.33		V
I_IH	Input high level input leakage current	V_IN = VCC		90		μA
I_IL	Input low level input leakage	V_IN = GND		–90		μA
R_IND	Input pins pull down resistance	see Detailed Description for more information	28.5	55	113	kΩ
R_INU	Input pins pull up resistance	see Detailed Description for more information	28.5	55	113	kΩ
T_INFIL	IN+, IN– and RST/EN deglitch (ON and OFF) filter time	f_S = 50kHz	28	40	60	ns
T_RSTFIL	Deglitch filter time to reset /FLT		400	650	800	ns
GATE DRIVER STAGE
I_OUT, I_OUTH	Peak source current	C_L=0.18μF, f_S=1kHz		10		A
I_OUT, I_OUTL	Peak sink current	C_L=0.18μF, f_S=1kHz		10		A
R_OUTH^⁽³⁾	Output pull-up resistance	I_OUT = –0.1A	1.5	2.5	4.9	Ω
R_OUTL	Output pull-down resistance	I_OUT = 0.1A	0.1	0.3	0.7	Ω
V_OUTH	High level output voltage	I_OUT = –0.2A, V_DD=18V		17.5		V
V_OUTL	Low level output voltage	I_OUT = 0.2A		60		mV
ACTIVE PULLDOWN
V_OUTPD	Output active pull down on OUT, OUTL	I_OUTL or I_OUT = 0.1×I_OUT(L)(tpy), VDD=OPEN, VEE=COM	1.5	2	2.5	V
INTERNAL ACTIVE MILLER CLAMP
V_CLMPTH	Miller clamp threshold voltage	Reference to VEE	1.5	2.0	2.5	V
V_CLMPI	Output low clamp voltage	I_CLMPI = 1A		VEE + 0.5		V
I_CLMPI	Output low clamp current	V_CLMPI = 0V, VEE = –2.5V		4		A
R_CLMPI	Miller clamp pull down resistance	I_CLMPI = 0.2A		0.6		Ω
t_DCLMPI	Miller clamp ON delay time	C_L = 1.8nF		15	50	ns
SHORT CIRCUIT CLAMPING
V_CLP-OUT(H)	V_OUT–VDD, V_OUTH–VDD	OUT = Low, I_OUT(H) = 500mA, t_CLP=10us		0.9		V
V_CLP-OUT(L)	V_OUT–VDD, V_OUTL–VDD	OUT = High, I_OUT(L) = 500mA, t_CLP=10us		1.8		V
V_CLP-CLMPI	V_CLMPI–VDD	OUT = High, I_CLMPI = 20mA, t_CLP=10us		1.0		V
OC PROTECTION
I_DCHG	OC pull down current when	V_OC = 1V		40		mA
V_OCTH	Detection Threshold		0.63	0.7	0.77	V
V_OCL	Voltage when OUT(L) = LOW, Reference to COM	I_OC = 5mA		0.13		V
t_OCFIL	OC fault deglitch filter		95	120	180	ns
t_OCOFF	OC propagation delay to OUT(L) 90%		150	270	400	ns
t_OCFLT	OC to FLT low delay		300	530	750	ns
INTERNAL SOFT TURN-OFF
I_STO	Soft turn-off current on fault conditions	V_DD-V_EE=20V, V_OUTL-COM=8V	250	400	570	mA
ISOLATED TEMPERATURE SENSE AND MONITOR (AIN–APWM)
V_AIN	Analog sensing voltage range		0.6		4.5	V
I_AIN	Internal current source	V_AIN=2.5V, -40°C< T_J< 150°C	196	200	209	μA
f_APWM	APWM output frequency	V_AIN=2.5V	380	400	420	kHz
BW_AIN	AIN–APWM bandwidth			10		kHz
D_APWM	APWM Dutycycle	V_AIN = 0.6V	86.5	88	89.5	%
		V_AIN = 2.5V	48.5	50	51.5
		V_AIN = 4.5V	7.5	10	11.5
FLT AND RDY REPORTING
t_RDYHLD	VDD UVLO RDY low minimum holding time		0.55		1	ms
t_FLTMUTE	Output mute time on fault	Reset fault through RST/EN	0.55		1	ms
R_ODON	Open drain output on resistance	I_ODON = 5mA		30		Ω
V_ODL	Open drain low output voltage	IODON = 5mA			0.3	V
COMMON MODE TRANSIENT IMMUNITY
CMTI	Common-mode transient immunity		150			V/ns

(1) Current are positive into and negative out of the specified terminal.

(2) All voltages are referenced to COM unless otherwise notified.

(3) For internal PMOS only. Refer to Feature Description for effective pull-up resistance.