ZHCSRQ4 august 2023 TPSM8S6C24
PRODUCTION DATA
| CMD Address | 80h |
| Write Transaction: | Write Byte |
| Read Transaction: | Read Byte |
| Format: | Unsigned Binary (1 byte) |
| Phased: | Yes |
| NVM Back-up: | No |
| Updates: | On-the-fly |
The STATUS_MFR_SPECIFIC command returns one data byte with contents regard of communications, logic, and memory as follows. All supported bits may be cleared either by CLEAR_FAULTS, or individually by writing 1b to the (80h) STATUS_MFR_SPECIFIC register in their position, per the PMBus 1.3.1 Part II specification section 10.2.4.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RW | R | R | R | RW | RW | RW | R |
| POR | SELF | 0 | 0 | RESET | BCX | SYNC | 0 |
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 7 | POR | RW | 0b | 0: No Power-On Reset Fault has been detected. 1: A Power-On Reset Fault has been detected. This bit must be set if: Power-On Self-Check of Internal Trim values, USER_STORE NVM check-sum, or Pin Detection reports an invalid result. |
| 6 | SELF | R | 0b | LIVE (unlatched) status bit. Showing the status of the Power-On Self-Check. 0b: Power On Self-Check is complete. All expected BCX Loop Followers have responded. 1b: Power-On Self-Check is in progress. One or more BCX Loop Followers have not responded. |
| 5:4 | Not supported | R | 00b | Not supported and always set to 00b. |
| 3 | RESET | RW | 0b: | 0b: A RESET_ VOUT event has NOT occurred. 1b: A RESET_ VOUT event has occurred. |
| 2 | BCX | RW | 0b | 0b: A BCX fault event has NOT occurred. 1b: A BCX fault event has occurred. |
| 1 | SYNC | RW | 0b | 0b: No SYNC fault has been detected. 1b: A SYNC fault has been detected. |
| 0 | Not supported | R | 0b | Not supported and always set to 0b. |
Per the PMBus Spec writing a 1 to any bit in a STATUS register shall clear that bit if it is set. All bits which may trigger SMBALERT have a corresponding bit in SMBALERT_MASK.