ZHCSPT6D July 2023 – June 2024 TPSM8287A06 , TPSM8287A10 , TPSM8287A12 , TPSM8287A15
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| SUPPLY | |||||||
| IQ_VIN | Quiescent current (VIN) | EN = high, IOUT = 0 mA, V(SW) = 0 V, SINGLE=1, MODE/SYNC = low, device not switching, TJ = 25 °C | 1.5 | 3 | mA | ||
| ISD | Shutdown current (VIN) | EN = low, V(SW) = 0 V, TJ = 25 °C | 16.5 | 40 | μA | ||
| VIT+(UVLO) | Positive-going UVLO threshold voltage (VIN) | 2.5 | 2.6 | 2.7 | V | ||
| VIT–(UVLO) | Negative-going UVLO threshold voltage (VIN) | 2.4 | 2.5 | 2.6 | V | ||
| Vhys(UVLO) | UVLO hysteresis voltage (VIN) | 90 | mV | ||||
| VIT+(OVLO) | Positive-going OVLO threshold voltage (VIN) | 6.1 | 6.3 | 6.5 | V | ||
| VIT–(OVLO) | Negative-going OVLO threshold voltage (VIN) | 6.0 | 6.2 | 6.4 | V | ||
| Vhys(OVLO) | OVLO hysteresis voltage (VIN) | 85 | mV | ||||
| VPOR– | Negative-going power-on reset (POR) threshold (VIN) | 1.4 | V | ||||
| TSD | Thermal shutdown threshold temperature | TJ rising | 170 | °C | |||
| Thermal shutdown hysteresis | 20 | °C | |||||
| TW | Thermal warning threshold temperature | TJ rising | 150 | °C | |||
| Thermal warning hysteresis | 20 | °C | |||||
| CONTROL and INTERFACE | |||||||
| VIT+ | Positive-going input threshold voltage (EN) | 0.97 | 1.0 | 1.03 | V | ||
| VIT– | Negative-going input threshold voltage (EN) | 0.87 | 0.9 | 0.93 | V | ||
| Vhys | Hysteresis voltage (EN) | 95 | mV | ||||
| IIH | High-level input current (EN) | VEN = VIN, internal pulldown resistor disabled | 200 | nA | |||
| IIL | Low-level input current (EN) | VEN = 0 V, internal pulldown resistor disabled | –200 | nA | |||
| VIH | High-level input voltage (SDA, SCL, MODE/SYNC) | 0.8 | V | ||||
| VIL | Low-level input voltage (SDA, SCL, MODE/SYNC) | 0.4 | V | ||||
| VOL | Low-level output voltage (SDA) | IOL = 9 mA | 0.4 | V | |||
| IOL = 5 mA | 0.2 | V | |||||
| ILKG | Input leakage current into SDA, SCL | VOH = 3.3 V | 200 | nA | |||
| IIL | Low-level input current (MODE/SYNC) | VMODE/SYNC = 0 V | –150 | 150 | nA | ||
| IIH | High-level input current (MODE/SYNC) | VMODE/SYNC = VIN | 3 | μA | |||
| td(EN)1 | Enable delay time when EN tied to VIN | Measured from when EN goes high to when device starts switching SRVIN = 1 V/μs |
210 | 535 | μs | ||
| td(EN)2 | Enable delay time when VIN already applied | Measured from when EN goes high to when device starts switching | 40 | 100 | μs | ||
| td(RAMP) | Output voltage ramp time | Measured from when device starts switching to rising edge of PG. Selectable with I2C. See Table 8-5. | 0.46 | 0.54 | 0.62 | ms | |
| 0.88 | 1.04 | 1.20 | ms | ||||
| 1.73 | 2.04 | 2.35 | ms | ||||
| 3.43 | 4.04 | 4.65 | ms | ||||
| TSYNC_LOCK | Time to lock external frequency | 50 | μs | ||||
| f(SYNC) | Synchronization clock frequency range (MODE/SYNC) | TPSM8287A06BAS, TPSM8287A10BAH, TPSM8287A12BAS, TPSM8287A15BAH |
1.3 | 2.0 | MHz | ||
| f(SYNC) | Synchronization clock frequency range (MODE/SYNC) | TPSM8287A12BBS, TPSM8287A15BBH | 1.8 | 2.7 | MHz | ||
| D(SYNC) | Synchronization clock duty cycle range (MODE/SYNC) | 45 | 55 | ||||
| VT+(UVP) | Positive-going power good threshold voltage (output undervoltage) | 94 | 96 | 98 | %VOUT | ||
| VT–(UVP) | Negative-going power good threshold voltage (output undervoltage) | 92 | 94 | 96 | %VOUT | ||
| VT+(OVP) | Positive-going power good threshold voltage (output overvoltage) | 104 | 106 | 108 | %VOUT | ||
| VT–(OVP) | Negative-going power good threshold voltage (output overvoltage) | 102 | 104 | 106 | %VOUT | ||
| VOL | Low-level output voltage (PG) | IOL = 10 mA | 0.3 | V | |||
| ILKG | Input leakage current into PG | VOH = 3.3 V | 200 | nA | |||
| VIH | High-level input voltage (PG) | Device configured as a secondary device in stacked operation | 0.8 | V | |||
| VIL | Low-level input voltage (PG) | Device configured as a secondary device in stacked operation | 0.4 | V | |||
| IIH | High-level input current (PG) | Device configured as a secondary device in stacked operation | 1 | μA | |||
| IIL | Low-level input current (PG) | Device configured as a secondary device in stacked operation | –1 | μA | |||
| td(PG) | Deglitch time (PG) | High-to-low or low-to-high transition on the PG pin | 34 | 40 | 46 | μs | |
| OUTPUT | |||||||
| VOUT | Output voltage accuracy | VIN ≥ VOUT + 1.4 V | –0.8 | 0.8 | % | ||
| VICR | Input common-mode range (VOSNS) | –100 | VO(nom) + 100 | mV | |||
| VICR | Input common-mode range (GOSNS) | –100 | 100 | mV | |||
| fSW | Switching frequency (SW) | fSW = 1.5 MHz, PWM operation, VIN = 3.3 V, VOUT = 0.75 V | 1.35 | 1.5 | 1.65 | MHz | |
| fSW = 2.25 MHz, PWM operation, VIN = 3.3 V, VOUT = 0.75 V | 2.025 | 2.25 | 2.475 | ||||
| fmod | Frequency of the spread-spectrum sweep | fsw/2048 | kHz | ||||
| ΔfSW | Switching frequency variation during spread-spectrum operation | ±10% | |||||
| τ | Emulated current time constant | 12.5 | μs | ||||
| gm | Error amplifier transconductance | 1.5 | mS | ||||
| ILIM | High-side FET forward switch current limit, DC | TPSM8287A06BAS | 8 | 11 | 13 | A | |
| TPSM8287A10BAH | 14.5 | 17.5 | 19.5 | ||||
| TPSM8287A12BAS, TPSM8287A12BBS | 15 | 19 | 21 | ||||
| TPSM8287A15BAH, TPSM8287A15BBH | 18 | 23 | 25 | ||||
| Low-side FET negative current limit, DC | 7.5 | 12 | A | ||||