ZHCSPT6D July 2023 – June 2024 TPSM8287A06 , TPSM8287A10 , TPSM8287A12 , TPSM8287A15
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Device Options
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Fixed-Frequency DCS-Control Topology
- 7.3.2 Forced-PWM and Power-Save Modes
- 7.3.3 Precise Enable
- 7.3.4 Start-Up
- 7.3.5 Switching Frequency Selection
- 7.3.6 Output Voltage Setting
- 7.3.7 Compensation (COMP)
- 7.3.8 Mode Selection / Clock Synchronization (MODE/SYNC)
- 7.3.9 Spread Spectrum Clocking (SSC)
- 7.3.10 Output Discharge
- 7.3.11 Undervoltage Lockout (UVLO)
- 7.3.12 Overvoltage Lockout (OVLO)
- 7.3.13 Overcurrent Protection
- 7.3.14 Power Good (PG)
- 7.3.15 Remote Sense
- 7.3.16 Thermal Warning and Shutdown
- 7.3.17 Stacked Operation
- 7.4 Device Functional Modes
- 7.5 Programming
- 8 Device Registers
-
9 Application and Implementation
- 9.1 Application Information
- 9.2 Typical Application
- 9.3 Typical Application Using Four TPSM8287Axx in Parallel Operation
- 9.4 Power Supply Recommendations
- 9.5 Layout
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
7.3.14.1 Power-Good Standalone, Primary Device Behavior
The primary purpose of the PG pin is to indicate if the output voltage is in regulation, but it also indicates if the device is in thermal shutdown or disabled. Table 7-5 summarizes the behavior of the PG pin in a stand-alone or primary device.
| VIN | EN | VOUT | Soft Start | PGBLNKDVS | TJ | PG |
|---|---|---|---|---|---|---|
VIN < 2 V | X | X | X | X | X | Undefined |
| VIT-(UVLO) ≥ VIN ≥ 2 V | X | X | X | X | X | Low |
| VIT-(OVLO) > VIN > VIT+(UVLO) | L | X | X | X | X | Low |
| H | X | Active | X | X | Low | |
| VOUT > VT+(OVP) or VOUT < VT-(UVP) | Inactive | 0 | X | Low | ||
1 (DVS inactive) | X | Low | ||||
X | 1 (DVS active) | TJ < TSD | Hi-Z | |||
| VT-(OVP) > VOUT > VT+(UVP) | X | Hi-Z | ||||
| X | X | X | TJ > TSD | Low | ||
VIN > VIT+(OVLO) | X | X | X | X | X | Low |
Figure 7-21 shows a functional block diagram of the power-good function in a stand-alone or primary device. A window comparator monitors the output voltage, and the output of the comparator goes high if the output voltage is either less than 94% (typical) or greater than 106% (typical) of the nominal output voltage. The output of the window comparator is deglitched – the typical deglitch time is 40 μs (see Figure 7-20) – and then used to drive the open-drain PG pin.
Figure 7-20 Power-Good Transient and Delay BehaviorIf an output under or overvoltage event occurs, the device sets the PBUV or PBOV bits in the STATUS register, respectively. The device clears the PBOV and PBUV bits if the user reads the STATUS register after the power-bad condition no longer exists.
Figure 7-21 Power-Good Functional Block Diagram (Stand-Alone / Primary Device)
During DVS activity, when the device transitions from one output voltage setting to another, the output voltage can temporarily exceed the limits of the window comparator and pull the PG pin low. The device has a feature to disable this behavior: if PGBLNKDVS = 1 in the CONTROL3 register, the device ignores the output of the power-good window comparator while DVS is active.
Note that the PG pin is always low – regardless of the output of the window comparator – when:
- The device is in thermal shutdown
- The device is in Hiccup mode
- The device is disabled
- The device is in undervoltage or overvoltage lockout (UVLO or OVLO)
- The device is in soft start