ZHCSPT6D July 2023 – June 2024 TPSM8287A06 , TPSM8287A10 , TPSM8287A12 , TPSM8287A15
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Device Options
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Fixed-Frequency DCS-Control Topology
- 7.3.2 Forced-PWM and Power-Save Modes
- 7.3.3 Precise Enable
- 7.3.4 Start-Up
- 7.3.5 Switching Frequency Selection
- 7.3.6 Output Voltage Setting
- 7.3.7 Compensation (COMP)
- 7.3.8 Mode Selection / Clock Synchronization (MODE/SYNC)
- 7.3.9 Spread Spectrum Clocking (SSC)
- 7.3.10 Output Discharge
- 7.3.11 Undervoltage Lockout (UVLO)
- 7.3.12 Overvoltage Lockout (OVLO)
- 7.3.13 Overcurrent Protection
- 7.3.14 Power Good (PG)
- 7.3.15 Remote Sense
- 7.3.16 Thermal Warning and Shutdown
- 7.3.17 Stacked Operation
- 7.4 Device Functional Modes
- 7.5 Programming
- 8 Device Registers
-
9 Application and Implementation
- 9.1 Application Information
- 9.2 Typical Application
- 9.3 Typical Application Using Four TPSM8287Axx in Parallel Operation
- 9.4 Power Supply Recommendations
- 9.5 Layout
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
7.3.4 Start-Up
When the voltage on the VIN pin exceeds the positive-going UVLO threshold, the device initializes as follows:
- The device pulls the EN pin low
- The device the internal reference voltage
- The device reads the state of the VSETx and SYNC_OUT pins
- The device loads the default values into the device registers
When initialization is complete, the device enables I2C communication and releases the EN pin. The external circuitry controlling the EN pin now determines the behavior of the device:
- If the EN pin is low, the device is disabled:
- The user can write to and read from the device registers
- The power stage does not operate (high-impedance).
- If the EN pin is high, the device is enabled:
- The user can write to and read from the device registers
- After a short delay, the power stage starts switching
- The converter ramps up the output voltage
Figure 7-11 Start-Up Timing When EN is Pulled Up to VIN
Figure 7-12 shows the start-up sequence when an external signal is connected to the EN pin.
Figure 7-12 Start-Up Timing When an External Signal is Connected to the EN Pin
The SSTIME[1:0] bits in the CONTROL2 register select the duration of the soft-start ramp:
- td(RAMP) = 500 μs
- td(RAMP) = 1 ms (default)
- td(RAMP) = 2 ms
- td(RAMP) = 4 ms
- Output voltage setpoint (VOUT[7:0])
- Output voltage range (VRANGE[1:0])
- Soft-start time (SSTIME[1:0])
If the user changes the value of VSET[7:0] during soft start, the device first ramps to the value that VSET[7:0] had when the soft-start sequence began. When soft start is complete, the device ramps up or down to the new value.
During start-up, the device does not sink current to make sure that the output voltage follows the configured ramp rate to the target output voltage. With this, the device can start up into a prebiased output. In this case, only a portion of the internal voltage ramp is seen externally (see Figure 7-13).
Figure 7-13 Start-Up into a Prebiased Output