ZHCSPT6D July 2023 – June 2024 TPSM8287A06 , TPSM8287A10 , TPSM8287A12 , TPSM8287A15
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Device Options
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Fixed-Frequency DCS-Control Topology
- 7.3.2 Forced-PWM and Power-Save Modes
- 7.3.3 Precise Enable
- 7.3.4 Start-Up
- 7.3.5 Switching Frequency Selection
- 7.3.6 Output Voltage Setting
- 7.3.7 Compensation (COMP)
- 7.3.8 Mode Selection / Clock Synchronization (MODE/SYNC)
- 7.3.9 Spread Spectrum Clocking (SSC)
- 7.3.10 Output Discharge
- 7.3.11 Undervoltage Lockout (UVLO)
- 7.3.12 Overvoltage Lockout (OVLO)
- 7.3.13 Overcurrent Protection
- 7.3.14 Power Good (PG)
- 7.3.15 Remote Sense
- 7.3.16 Thermal Warning and Shutdown
- 7.3.17 Stacked Operation
- 7.4 Device Functional Modes
- 7.5 Programming
- 8 Device Registers
-
9 Application and Implementation
- 9.1 Application Information
- 9.2 Typical Application
- 9.3 Typical Application Using Four TPSM8287Axx in Parallel Operation
- 9.4 Power Supply Recommendations
- 9.5 Layout
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RDW|39
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購信息
7.5.2 Standard-, Fast-, Fast-Mode Plus Protocol
The controller initiates a data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 7-23. All I2C-compatible devices must recognize a start condition.
Figure 7-23 START and
STOP ConditionsThe controller then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the controller makes sure that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 7-24). All devices recognize the address sent by the controller and compare it to the internal fixed addresses. Only the target with a matching address generates an acknowledge (see Figure 7-25) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the controller knows that communication link with a target has been established.
Figure 7-24 Bit
Transfer on the Serial Interface
Figure 7-25 Acknowledge on the I2C BusThe controller generates further SCL cycles to either transmit data to the target (R/W bit 0) or receive data from the target (R/W bit 1). In either case, the target must acknowledge the data sent by the controller. So an acknowledge signal can either be generated by the controller or by the target, depending on which one is the receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary (see Figure 7-26).
Figure 7-26 Bus ProtocolTo signal the end of the data transfer, the controller generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 7-23). This action releases the bus and stops the communication link with the addressed target. All I2C-compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and the devices wait for a start condition followed by a matching address.
Attempting to read data from register addresses not listed in this section results in 0x00 being read out.