ZHCSLB3B April 2020 – May 2025 TPS7B84-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Pin Configuration and Functions
- 5 Specifications
- 6 Detailed Description
-
7 Application and Implementation
- 7.1 Application Information
- 7.2 Typical Application
- 7.3 Power Supply Recommendations
- 7.4 Layout
- 8 Device and Documentation Support
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
封裝選項
請參考 PDF 數據表獲取器件具體的封裝圖。
機械數據 (封裝 | 引腳)
- DCY|4
- DRB|8
散熱焊盤機械數據 (封裝 | 引腳)
- DRB|8
訂購信息
7.1.6.2 Power Dissipation vs Ambient Temperature
Figure 7-6 is based off of a JESD51-7 4 layer high-K board. The allowable power dissipation was estimated using the following equation. As disscussed in the An empirical analysis of the impact of board layout on LDO thermal performance application report, thermal dissipation can be improved in the JEDEC high-K layout by adding top layer copper and increasing the number of thermal vias. If a good thermal layout is used, the allowable thermal dissipation can be improved by up to 50%.
Equation 8. 
Figure 7-6 TPS7B84-Q1 Allowable Power
Dissipation